Hypergraph partitioning with fixed vertices

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Hypergraph partitioning with fixed vertices

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 355 - 359

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Andrew E. Caldwell	UCLA Computer Science Department, Los Angeles, CA
Andrew B. Kahng	UCLA Computer Science Department, Los Angeles, CA
Igor L. Markov	UCLA Computer Science Department, Los Angeles, CA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 9, Citation Count: 4

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	C.J. Alpert, "Partitioning Benchmarks for VLSI CAD Community", http ://vls ~cad. cs. ucla. edu/~ cheese/benchmarks, html
	2	Charles J. Alpert, The ISPD98 circuit benchmark suite, Proceedings of the 1998 international symposium on Physical design, p.80-85, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274546]
	3	Charles J. Alpert , Jen-Hsin Huang , Andrew B. Kahng, Multilevel circuit partitioning, Proceedings of the 34th annual conference on Design automation, p.530-533, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266275]
	4	Charles J. Alpert , Andrew B. Kahng, Recent directions in netlist partitioning: a survey, Integration, the VLSI Journal, v.19 n.1-2, p.1-81, Aug. 1995 [doi>10.1016/0167-9260(95)00008-4]
	5	J. A. Davis, V. K. De and J. D. Meindl, "A Stochastic Wire-Length Distribution for Gigascale Integration (GSI) - Part I: Derivation and Validation", IEEE Transactions on Electron Devices, vol. 45(3), pp. 580-589.
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	7	Shantanu Dutt , Wenyong Deng, VLSI circuit partitioning by cluster-removal using iterative improvement techniques, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.194-200, November 10-14, 1996, San Jose, California, United States
	8	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Proceedings of the 19th conference on Design automation, p.175-181, January 1982
	9	Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
	10	M.K. Goldberg and M. Burstein, "Heuristic Improvement Technique for Bisection of VLSI Networks", IEEE Transactions on Computer- Aided Design, 1983, pp. 122-125.
	11	S. Hauck and G. Borriello, "An Evaluation of Bipartitioning Techniques", IEEE Transactions on Computer-Aided Design 16(8) (1997), pp. 849-866.
	12	Dennis J.-H. Huang , Andrew B. Kahng, Partitioning-based standard-cell global placement with an exact objective, Proceedings of the 1997 international symposium on Physical design, p.18-25, April 14-16, 1997, Napa Valley, California, United States [doi>10.1145/267665.267674]
	13	B. W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs", Bell System Tech. Journal 49 (1970), pp. 291- 307.
	14	George Karypis , Rajat Aggarwal , Vipin Kumar , Shashi Shekhar, Multilevel hypergraph partitioning: application in VLSI domain, Proceedings of the 34th annual conference on Design automation, p.526-529, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266273]
	15	B. Landman and R. Russo, "On a Pin Versus Block Relationship for Partitioning of Logic Graphs", IEEE Transactions on Computers C- 20(12) (1971), pp. 1469-1479.
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	17	Dennis Sylvester , Kurt Keutzer, Getting to the bottom of deep submicron, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.203-211, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288614]

CITED BY 4

	Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Improved algorithms for hypergraph bipartitioning, Proceedings of the 2000 conference on Asia South Pacific design automation, p.661-666, January 2000, Yokohama, Japan
	Min Ouyang , Michel Toulouse , Krishnaiyan Thulasiraman , Fred Glover , Jitender S. Deogun, Multilevel cooperative search: application to the circuit/hypergraph partitioning problem, Proceedings of the 2000 international symposium on Physical design, p.192-198, May 2000, San Diego, California, United States
	Andrew E. Caldwell , Andrew B. Kahng , Andrew A. Kennings , Igor L. Markov, Hypergraph partitioning for VLSI CAD: methodology for heuristic development, experimentation and reporting, Proceedings of the 36th ACM/IEEE conference on Design automation, p.349-354, June 21-25, 1999, New Orleans, Louisiana, United States
	Chanseok Hwang , Massoud Pedram, PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China