Power efficient mediaprocessors

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Power efficient mediaprocessors: design space exploration

Full text

Pdf (148 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 321 - 326

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Johnson Kin	Department of Electrical Enginerring, UCLA
Chunho Lee	Department of Computer Science, UCLA
William H. Mangione-Smith	Department of Electrical Enginerring, UCLA
Miodrag Potkonjak	Department of Computer Science, UCLA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 31, Citation Count: 8

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/309847.309943 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Sanjeev Banerjia , William A. Havanki , Thomas M. Conte, Treegion Scheduling for Highly Parallel Processors, Proceedings of the Third International Euro-Par Conference on Parallel Processing, p.1074-1078, August 26-29, 1997
	2	A. R Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R. Broderson. Optimizing power using transformations. IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, 14(1): 12, 1995.
	3	A. R Chandrakasan, S. Sheng, and R. W. Broderson. Low-power CMOS digital design. IEEE Journal of Solid-State Circuits, 27(4):473-484, 1992.
	4	A. R Chandrakasan, M. Srivastava, and R. Broderson. Energy efficient programmable computation. In VLSI Design Conference, pages 261-264, 1994.
	5	Pohua P. Chang , Scott A. Mahlke , William Y. Chen , Nancy J. Warter , Wen-mei W. Hwu, IMPACT: an architectural framework for multiple-instruction-issue processors, Proceedings of the 18th annual international symposium on Computer architecture, p.266-275, May 27-30, 1991, Toronto, Ontario, Canada
	6	A. Chatterjee and R. Roy. Synthesis of low power DSP circuits using activity metrics. In VLSIDesign Conference, pages 265-270, 1994.
	7	Robert P. Colwell , Robert P. Nix , John J. O'Donnell , David B. Papworth , Paul K. Rodman, A VLIW architecture for a trace scheduling compiler, Proceedings of the second international conference on Architectual support for programming languages and operating systems, p.180-192, October 1987, Palo Alto, California, United States
	8	J.A. Fisher. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computing, C-30:478-490, 1981.
	9	Michael J. Flynn, Computer Architecture: Pipelined and Parallel Processor Design, Jones and Bartlett Publishers, Inc., 1995
	10	Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
	11	Laurence Goodby , Alex Orailoglu , Paul M. Chau, Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.323-326, October 10-12, 1994
	12	Craig Hansen, MicroUnity's MediaProcessor Architecture, IEEE Micro, v.16 n.4, p.34-41, August 1996 [doi>10.1109/40.526923]
	13	John L. Hennessy , David A. Patterson, Computer architecture (2nd ed.): a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1996
	14	Inki Hong , Miodrag Potkonjak , Ramesh Karri, Power optimization using divide-and-conquer techniques for minimization of the number of operations, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.108-111, November 09-13, 1997, San Jose, California, United States
	15	R Y. Hsu. Highly concurrent scalar processing. Technical Report CSG-49, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1986.
	16	R. Jain. The Art of Computer Systems Pelformance Analysis. Wiley, 1991.
	17	Paul Kalapathy, Hardware-Software Interactions on Mpact, IEEE Micro, v.17 n.2, p.20-26, March 1997 [doi>10.1109/40.592309]
	18	A. Kalavade and E.A. Lee. Complexity management in system-level design. Journal of VLSI Signal P1vcessing, 14(2): 157-169, 1996.
	19	Milind B. Kamble , Kanad Ghose, Analytical energy dissipation models for low-power caches, Proceedings of the 1997 international symposium on Low power electronics and design, p.143-148, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263310]
	20	Johnson Kin , Munish Gupta , William H. Mangione-Smith, The filter cache: an energy efficient memory structure, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.184-193, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	21	Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	22	Ruby B. Lee , Michael D. Smith, Guest Editors' Introduction: Media Processing: A New Design Target, IEEE Micro, v.16 n.4, p.6-9, August 1996 [doi>10.1109/MM.1996.526920]
	23	Wen-Mei W. Hwu , Scott A. Mahlke , William Y. Chen , Pohua P. Chang , Nancy J. Warter , Roger A. Bringmann , Roland G. Ouellette , Richard E. Hank , Tokuzo Kiyohara , Grant E. Haab , John G. Holm , Daniel M. Lavery, The superblock: an effective technique for VLIW and superscalar compilation, The Journal of Supercomputing, v.7 n.1-2, p.229-248, May 1993 [doi>10.1007/BF01205185]
	24	Scott A. Mahlke , David C. Lin , William Y. Chen , Richard E. Hank , Roger A. Bringmann, Effective compiler support for predicated execution using the hyperblock, Proceedings of the 25th annual international symposium on Microarchitecture, p.45-54, December 01-04, 1992, Portland, Oregon, United States
	25	J. Montanaro et al. A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. IEEE Journal of Solid-State Circuits, 31(11): 1703-1714, November 1996.
	26	Alex Peleg , Uri Weiser, MMX Technology Extension to the Intel Architecture, IEEE Micro, v.16 n.4, p.42-50, August 1996 [doi>10.1109/40.526924]
	27	Anand Raghunathan , Niraj K. Jha, Behavioral Synthesis for low Power, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.318-322, October 10-12, 1994
	28	D. Singh, J. Rabaey, M.Pedram, F. Catthoor, S. Rajgopal, N. Sehgal, and T. Mozdzen. Power conscious CAD tools and methodologies: A perspective. P1vceedings of lEEE, 83(4):570-594, 1995.
	29	Mani B. Srivastava , Anantha P. Chandrakasan , R. W. Brodersen, Predictive system shutdown and other architectural techniques for energy efficient programmable computation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.4 n.1, p.42-55, March 1996 [doi>10.1109/92.486080]
	30	Vivek Tiwari , Sharad Malik , Andrew Wolfe, Power analysis of embedded software: a first step towards software power minimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.437-445, Dec. 1994 [doi>10.1109/92.335012]
	31	J. Turley and H. Hakkarainen. TI's new 'C6x DSP screams at 1,600 MIPS. The Miclvplvcessor Report, 11:14-17, 1997.

CITED BY 8

	Reiner Hartenstein, Coarse grain reconfigurable architecture (embedded tutorial), Proceedings of the 2001 conference on Asia South Pacific design automation, p.564-570, January 2001, Yokohama, Japan
	Manoj Kumar Jain , M. Balakrishnan , Anshul Kumar, An efficient technique for exploring register file size in ASIP synthesis, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
	R. Hartenstein, A decade of reconfigurable computing: a visionary retrospective, Proceedings of the conference on Design, automation and test in Europe, p.642-649, March 2001, Munich, Germany
	Diana Marculescu , Anoop Iyer, Application-driven processor design exploration for power-performance trade-off analysis, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Sridhar Rajagopal , Joseph R. Cavallaro , Scott Rixner, Design Space Exploration for Real-Time Embedded Stream Processors, IEEE Micro, v.24 n.4, p.54-66, July 2004
	Matthias Gries, Methods for evaluating and covering the design space during early design development, Integration, the VLSI Journal, v.38 n.2, p.131-183, December 2004
	Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000
	Vishal P. Bhatt , M. Balakrishnan , Anshul Kumar, Exploring the Number of Register Windows in ASIP Synthesis, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.233, January 07-11, 2002