Symbolic model checking using SAT procedures instead of BDDs

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Symbolic model checking using SAT procedures instead of BDDs

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 317 - 320

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

A. Biere	Computer Science Department, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA and Verysys Design Automation, Inc., 42707 Lawrence Place, Fremont, CA
A. Cimatti	Istituto per la Ricerca Scientifica e Tecnolgica (IRST), via Sommarive 18, 38055 Povo (TN), Italy
E. M. Clarke	Computer Science Department, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA and Verysys Design Automation, Inc., 42707 Lawrence Place, Fremont, CA
M. Fujita	Fujitsu Laboratories of America, Inc., 595 Lawrence Expressway, Sunnyvale, CA
Y. Zhu	Computer Science Department, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA and Verysys Design Automation, Inc., 42707 Lawrence Place, Fremont, CA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 52, Citation Count: 92

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	Richard Raimi , Jacob Abraham, Detecting false timing paths: experiments on PowerPC microprocessors, Proceedings of the 36th ACM/IEEE conference on Design automation, p.737-741, June 21-25, 1999, New Orleans, Louisiana, United States
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