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Performance-driven scheduling with bit-level chaining
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents
New Orleans, Louisiana, United States
Pages: 286 - 291  
Year of Publication: 1999
ISBN:1-58133-109-7
Authors
Sanghun Park  School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea
Kiyoung Choi  School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
K. S. Hwang, A. E. Casavant, C. T. Chang, and M. A. d'Abreu, "Scheduling and hardware sharing in pipelined data paths," in Proc. Int'l Conf. on Computer Aided Design, 1989, pp. 24-27.
 
2
N. Park and A. C. Parker, "Sehwa: A software package for synthesis of pipelines from behavioral specifications," IEEE Trans. on Computer-Aided Design, pp. 356-370, Mar. 1988.
 
3
S. Devadas and A. R. Newton, "Data path synthesis from behavioral description: An algorithmic approach," in Proc. Int'l Symposium on Circuits and Systems, 1987, pp. 298-401.
 
4
M. R. Corazao, M. A. Khalaf, L. M. Guerra M. Potkonjak, and J. Rabaey, "Performance optimization using template mapping for datapath-intensive highlevel synthesis," IEEE Trans. on Computer-Aided Design, vol. 15, no. 8, pp. 877-888, Aug. 1996.
 
5
R Kanthamanon, G. R. Hellestrand, and R. L.K. Chart, "A context sensitive scheduling technique under resource constraints," in P1vc. Asia Pacific Conf. on Hardware Description Language, 1997, pp. 92-99.
 
6
 
7
S. Parameswaran, R Jha, and N. Dutt, "Resynthesizing controllers for minimum execution time," in Proc. Asia Pacific Conf. on Hardware Description Language, 1994, pp. 111-117.
 
8
 
9
S. Park and K. Choi, "Latency minimisation by system clock optimisation," lEE Elect~vnics Letters, vol. 34, no. 9, pp. 862-864, Apr. 1998.
 
10
R G. Paulin and J. R Knight, "Force-directed scheduling for the behavioral synthesis of asic's," IEEE Trans. on Computer-Aided Design, vol. 8, no. 6, pp. 661-679, June 1989.
 
11
W. F. J. Verhaegh, P. E. R. Lippens, E. H. L. Aarts J.H.M. Korst, J. L. van Meerbergen, and A. van der Weft, "Improved force-directed scheduling in highthroughput digital signal processing," IEEE Trans. on Computer-Aided Design, vol. 14, no. 8, pp. 945-960, Aug. 1995.
 
12
R. Camposano, "Path-based scheduling for synthesis," IEEE Trans. on Computer-AidedDesign, vol. 10, no. 1, pp. 85-93, Jan. 1991.
 
13
C.T. Hwang, J.H. Lee, and Y.C. Hsu, "A formal approach to the scheduling problem in high level synthesis," IEEE Trans. on Computer-Aided Design, vol. 10, no. 4, pp. 464-475, Apr. 1991.
 
14
 
15
 
16
S. Wu, "Hyper's hardware library," M.S. thesis, EECS Department, U.C. Berkeley, 1993-1995.
 
17
O. Bentz, "A hardware mapper for the hyper high level synthesis system," M.S. thesis, EECS Department, U.C. Berkeley, 1993.
 
18
S. Note, F. Catthoor, G. Goossens, and H. De Man, "Combined hardware selection and pipelining in high performance deat-path design," in P~vc. Int'l Conf. on Computer Design, 1990, pp. 328-331.
 
19
M. Potkonjak and J. Rabaey, "Retiming for scheduling," in P1vc. IEEE Workshop on VLSI Signal P1vcessing, 1990.
 
20
 
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22
S. Park and K. Choi, "Sequential circuit optimization by fsm transformation," in P1vc. Asia Pacific Conf. on Hardware Description Language, 1998, pp. 53-58.


Collaborative Colleagues:
Sanghun Park: colleagues
Kiyoung Choi: colleagues