A timing-driven soft-macro resynthesis method in interaction with chip floorplanning

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A timing-driven soft-macro resynthesis method in interaction with chip floorplanning

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 262 - 267

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Hsiao-Pin Su	Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan, ROC and Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, Taiwan, ROC
Allen C.-H. Wu	Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan, ROC
Youn-Long Lin	Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan, ROC

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 11, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 2

	Andrew B. Kahng, Classical floorplanning harmful?, Proceedings of the 2000 international symposium on Physical design, p.207-213, May 2000, San Diego, California, United States
	Alok Mehrotra , Lukas van Ginneken , Yatin Trivedi, Design flow and methodology for 50M gate ASIC, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan