Performance-driven integration of retiming and resynthesis

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Performance-driven integration of retiming and resynthesis

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 243 - 246

Year of Publication: 1999

ISBN:1-58133-109-7

Author

Peichen Pan

Strategic CAD Labs, Intel Corporation, Hillsboro, OR

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 6, Downloads (12 Months): 13, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. Bommu, M. Ciesielski, N. O'Neill, and P. Kalla. Retimingbased factorization for multi-level logic optimization. In Intl. Workshop on Logic Synthesis, 1997.
	2	Srimat T. Chakradhar , Sujit Dey , Miodrag Potkonjak , Steven G. Rothweiler, Sequential circuit delay optimization using global path delays, Proceedings of the 30th international conference on Design automation, p.483-489, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164991]
	3	Kuang-Chien Chen , Saburo Muroga, Timing optimization for multi-level combinational networks, Proceedings of the 27th ACM/IEEE conference on Design automation, p.339-344, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.105253]
	4	G. DeMicheli. Synchronous logic synthesis: algorithms for cycle-time minimization. IEEE Trans. on Computer-Aided Design, 10:63-73, 1991.
	5	Sujit Dey , Miodrag Potkonjak , Steven G. Rothweiler, Performance optimization of sequential circuits by eliminating retiming bottlenecks, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.504-509, November 1992, Santa Clara, California, United States
	6	S. Hassoun and C. Ebeling. Experiments in the iterative application of resynthesis and retiming. In Intl. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 1997.
	7	C. E. Leiserson and J. B. Saxe. Retiming synchronous circuitry. Algorithmica, 6:5-35, 1991.
	8	B. Lin. Restructuring of synchronous logic circuits. In European Conf. on Design Automation, pages 205-209, 1993.
	9	S. Malik, K. J. Singh, R. Brayton, and A. L. Sangiovanni- Vincentelli. Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. IEEE Trans. on Computer-Aided Design, 12:568-578, 1993.
	10	Peichen Pan , C. L. Liu, Optimal clock period FPGA technology mapping for sequential circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.3, p.437-462, July 1998 [doi>10.1145/293625.293632]
	11	K. J. Singh, A. R. Wang, R. Brayton, and A. L. Sangiovanni- Vincentelli. Timing optimization of combinational logic. In Intl. Conf. on Computer-Aided Design (ICCAD), pages 282- 285, 1988.
	12	H. J. Touati, H. Savoj, and R. K. Brayton. Delay optimization of combinational logic circuits by clustering and partial collapsing. In Intl. Conf. on Computer-Aided Design (1C- CAD), pages 188-191, 1991.