Maximizing performance by retiming and clock skew scheduling

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Maximizing performance by retiming and clock skew scheduling

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 231 - 236

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Xun Liu	Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan
Marios C. Papaefthymiou	Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan
Eby G. Friedman	Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 20, Citation Count: 4

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Srimat T. Chakradhar , Sujit Dey, Resynthesis and retiming for optimum partial scan, Proceedings of the 31st annual conference on Design automation, p.87-93, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196288]
	2	L.-E Chao and E. H.-M. Sha. Retiming and clock skew for synchronous systems. In Proc. International Syrup. on Circuits and Systems, pages 283-286, June 1994.
	3	R. B. Deokar and S. S. Sapatnekar. A graph-theoretic approach to clock skew optimization. In Proc. International Syrup. on Circuits and Systems, pages 407-410, May 1995.
	4	S. Dey and S. Chakradhar. Retiming sequential circuits to enhance testability. In Proc. 12th IEEE VLSI Test Syrup., pages 28-33, April 1994.
	5	John P. Fishburn, Clock Skew Optimization, IEEE Transactions on Computers, v.39 n.7, p.945-951, July 1990 [doi>10.1109/12.55696]
	6	E. G. Friedman. Clock Distribution Networks in VLSI Circuits and Systems. IEEE Press, 1995.
	7	Alexander T. Ishii , Charles E. Leiserson , Marios C. Papaefthymiou, Optimizing two-phase, level-clocked circuitry, Journal of the ACM (JACM), v.44 n.1, p.148-199, Jan. 1997 [doi>10.1145/256292.256301]
	8	Kumar N. Lalgudi , Marios C. Papaefthymiou, DELAY: an efficient tool for retiming with realistic delay modeling, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.304-309, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217546]
	9	C. E. Leiserson and J. B. Saxe. Retiming synchronous circuitry. A1- gorithmica, 6(1), 1991. Also available as MIT/LCS/TM-372.
	10	X. Liu, M. C. Papaefthymiou, and E. G. Friedman. Optimal clock skew scheduling tolerant to process variations. In Design, Automation, and Test in Europe, pages 643-649, March 1999.
	11	B. Lockyear and C. Ebeling. Optimal retiming of multi-phase, levelclocked circuits. In Advanced Research in VLSI and Parallel Systems: Proc. 1992 Brown/MIT Conf. MIT Press, March 1992.
	12	H.-G. Martin. Retiming by combination of relocation and clock delay adjustment. In Proc. European Design Automation Conf., pages 384- 389, September 1993.
	13	José Monteiro , Srinivas Devadas , Abhijit Ghosh, Retiming sequential circuits for low power, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.398-402, November 07-11, 1993, Santa Clara, California, United States
	14	José Luis Neves , Eby G. Friedman, Optimal clock skew scheduling tolerant to process variations, Proceedings of the 33rd annual conference on Design automation, p.623-628, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240636]
	15	Marios C. Papaefthymiou , Keith H. Randall, TIM: a timing package for two-phase, level-clocked circuitry, Proceedings of the 30th international conference on Design automation, p.497-502, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164998]
	16	Narendra V. Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Retiming of Circuits with Single Phase Transparent Latches, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.86-89, October 14-16, 1991
	17	T. Soyata, E. G. Friedman, and J. H. Mulligan, Jr. Incorporating interconnect, register, and clock distribution delays into the retiming process. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 16(1): 105-120, January 1997.

CITED BY 4

	Masahiko Toyonaga , Keiichi Kurokawa , Takuya Yasui , Atsushi Takahashi, A practical clock tree synthesis for semi-synchronous circuits, Proceedings of the 2000 international symposium on Physical design, p.159-164, May 2000, San Diego, California, United States
	M. Saitoh , M. Azuma , A. Takahashi, Clustering based fast clock scheduling for light clock-tree, Proceedings of the conference on Design, automation and test in Europe, p.240-245, March 2001, Munich, Germany
	Vaibhav Nawale , Thomas W. Chen, Optimal useful clock skew scheduling in the presence of variations using robust ILP formulations, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Vivek Joshi , David Blaauw , Dennis Sylvester, Soft-edge flip-flops for improved timing yield: design and optimization, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California