Soft scheduling in high level synthesis

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Soft scheduling in high level synthesis

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 219 - 224

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Jianwen Zhu	CECS, Information and Computer Science, University of California, Irvine, CA
Daniel D. Gajski	CECS, Information and Computer Science, University of California, Irvine, CA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 15, Citation Count: 8

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Daniel D. Gajski , Nikil D. Dutt , Allen C.-H. Wu , Steve Y.-L. Lin, High-level synthesis: introduction to chip and system design, Kluwer Academic Publishers, Norwell, MA, 1992
	2	J. Nestor and D.E Thomas. Behavioral Synthesis with Interfaces. Proceedings of the IEEE Conference on Computer Aided Design, November 1986.
	3	EG. Paulin, J.E Knight. Force-Directed Scheduling for the Behavioral Synthesis of ASIC's. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, June 1989.
	4	D. Ku, G. De Micheli. Relative Scheduling under Timing Constraints: Algorithms for High-Level Synthesis of Digital Circuits. IEEE Transactions on CAD/ICAS, Vol. 11, No. 6, April 1992.
	5	R. Camposano. Path-Based Scheduling for Synthesis. IEEE Transaction on CAD/ICAS, Vol. 10, No.l, January, 1991.
	6	Catherine H. Gebotys , Mohamed I. Elmasry, Simultaneous scheduling and allocation for cost constrained optimal architectural synthesis, Proceedings of the 28th conference on ACM/IEEE design automation, p.2-7, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127609]
	7	Birger Landwehr , Peter Marwedel , Rainer Dömer, OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming, Proceedings of the conference on European design automation, p.90-95, September 19-23, 1994, Grenoble, France
	8	Jen-Pin Weng , Alice C. Parker, 3D scheduling: high-level synthesis with floorplanning, Proceedings of the 28th conference on ACM/IEEE design automation, p.668-673, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127748]
	9	C. Ewering. Automatic High-Level Synthesis of Partitioned Busses. Proceedings of EuroDAC, 1990.
	10	Min Xu , F. J. Kurdahi, Layout-driven RTL binding techniques for high-level synthesis, Proceedings of the 9th international symposium on System synthesis, p.33, November 06-08, 1996
	11	Ron Cytron , Jeanne Ferrante , Barry K. Rosen , Mark N. Wegman , F. Kenneth Zadeck, Efficiently computing static single assignment form and the control dependence graph, ACM Transactions on Programming Languages and Systems (TOPLAS), v.13 n.4, p.451-490, Oct. 1991 [doi>10.1145/115372.115320]
	12	J. Zhu, D.D. Gajski. Soft Scheduling in High Level Synthesis. Technical Report ICS-98-37, Information and Computer Science, UC, Irvine, August, 1998.

CITED BY 8

	Mehrdad Reshadi , Daniel Gajski, A cycle-accurate compilation algorithm for custom pipelined datapaths, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
	Nelson L. Passos , Peng Xue , Hoang Bui, Instruction level parallelism of non-uniform acyclic loops, Journal of Computing Sciences in Colleges, v.19 n.4, p.279-286, April 2004
	R. Ruiz-Sautua , M. C. Molina , J. M. Mendías , R. Hermida, Arrival time aware scheduling to minimize clock cycle length, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Rafael Ruiz-Sautua , María C. Molina , José M. Mendías , Rom´n Hermida, Pre-synthesis optimization of multiplications to improve circuit performance, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	M. C. Molina , R. Ruiz-Sautua , J. M. Mendías , R. Hermida, Area optimization of multi-cycle operators in high-level synthesis, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	R. Ruiz-Sautua , M. C. Molina , J. M. Mendias , R. Hermida, Performance-driven read-after-write dependencies softening in high-level synthesis, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.7-12, November 06-10, 2005, San Jose, CA
	R. Ruiz-Sautua , M. C. Molina , J. M. Mendias , R. Hermida, Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis, Proceedings of the conference on Design, Automation and Test in Europe, p.1252-1257, March 07-11, 2005
	M. C. Molina , R. Ruiz-Sautua , P. García-Repetto , J. M. Mendías, Performance-driven scheduling of behavioural specifications, Integration, the VLSI Journal, v.42 n.3, p.294-303, June, 2009