Behavioral network graph

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Behavioral network graph: unifying the domains of high-level and logic synthesis

Full text

Pdf (787 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 213 - 218

Year of Publication: 1999

ISBN:1-58133-109-7

Author

Reinaldo A. Bergamaschi

IBM T. J. Watson Research Center, NY

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 6, Citation Count: 6

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/309847.309916 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	P. G. Paulin and J. P. Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's," IEEE Transactions on Computer-Aided Design, vol. CAD-8, pp. 661-679, June 1989.
	2	Reinaldo A. Bergamaschi , Salil Raje , Louise Trevillyan, Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.1, p.82-100, March 1997 [doi>10.1109/92.555989]
	3	M. C. McFarland, "The Value Trace: A data base for automated digital design," Tech. Rep. DRC-01-4-80, Design Research Center, Carnegie-Mellon University, December 1978.
	4	R. Camposano and It. M. Tabet, "Design representation for the synthesis of behavioral VHDL models," in Proceedings 9th International Symposium on Computer Hardware Description Languages and Their Applications, (Washington, D.C.), pp. 49-58, Elsevier Science Publishers B.V., June 1989.
	5	J. Darringer, W. Joyner, C. Berman, and L. Trevillyan, "Logic synthesis through local transformations," IBM Journal of Research and Development, vol. 25, July 1981.
	6	Richard Rudell, Design of a logic synthesis system (tutorial), Proceedings of the 33rd annual conference on Design automation, p.191-196, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240554]
	7	L. Stok , D. S. Kung , D. Brand , A. D. Drumm , L. N. Reddy , N. Hieter , D. J. Geiger , H. H. Chao , P. J. Osler , A. J. Sullivan, BooleDozer: logic synthesis for ASICs, IBM Journal of Research and Development, v.40 n.4, p.407-430, July 1996
	8	G. Goossens , J. Vandewlle , H. De Man, Loop optimization in register-transfer scheduling for DSP-systems, Proceedings of the 26th ACM/IEEE conference on Design automation, p.826-831, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74384]
	9	Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
	10	R.A. Bergamaschi and D. J. Allerton, "A graph.basedsilicon compiler for concurrent VLSI systems," in Proceedings of the IEEE CompEuro Conference, (Brussels), pp. 36-47, IEEE, April 1988.
	11	It. Camposano, "Path-based scheduling for synthesis," IEEE Transactions on Computer-Aided Design, vol. CAD-10, pp. 85-93, January 1991.
	12	K. O'Brien, M. Rahmouni, and A. Jerraya, "A VHDL-based scheduling algorithm for control-flow dominated circuits," in Sizth International Workshop on High-Level Synthesis, (Dana Point, CA), ACM, November 1992.

CITED BY 6

	Alex Doboli , Ranga Vemuri, Integrated high-level synthesis and power-net routing for digital design under switching noise constraints, Proceedings of the 38th conference on Design automation, p.629-634, June 2001, Las Vegas, Nevada, United States
	Sumit Gupta , Nick Savoiu , Nikil Dutt , Rajesh Gupta , Alex Nicolau, Conditional speculation and its effects on performance and area for high-level snthesis, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	W. O. Cesário , Z. Sugar , I. Moussa , A. A. Jerraya, Efficient integration of behavioral synthesis within existing design flows, Proceedings of the 13th international symposium on System synthesis, September 20-22, 2000, Madrid, Spain
	William E. Dougherty , Donald E. Thomas, Unifying behavioral synthesis and physical design, Proceedings of the 37th conference on Design automation, p.756-761, June 05-09, 2000, Los Angeles, California, United States
	Sumit Gupta , Rajesh Kumar Gupta , Nikil D. Dutt , Alexandru Nicolau, Coordinated parallelizing compiler optimizations and high-level synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.4, p.441-470, October 2004
	A. Chattopadhyay , B. Geukes , D. Kammler , E. M. Witte , O. Schliebusch , H. Ishebabi , R. Leupers , G. Ascheid , H. Meyr, Automatic ADL-based operand isolation for embedded processors, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany