Model order-reduction of RC(L) interconnect including variational analysis

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Model order-reduction of RC(L) interconnect including variational analysis

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 201 - 206

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Ying Liu	Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA
Lawrence T. Pileggi	Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA
Andrzej J. Strojwas	Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Avenue, Pittsburgh, PA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 15, Downloads (12 Months): 62, Citation Count: 30

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 30

	Ying Liu , Sani R. Nassif , Lawrence T. Pileggi , Andrzej J. Strojwas, Impact of interconnect variations on the clock skew of a gigahertz microprocessor, Proceedings of the 37th conference on Design automation, p.168-171, June 05-09, 2000, Los Angeles, California, United States
	Xuan Zeng , Dian Zhou , Wei Cai, An efficient DC-gain matched balanced truncation realization for VLSI Interconnect circuit order reduction, Microelectronic Engineering, v.60 n.1, p.3-15, January 2002
	Payam Heydari , Massoud Pedram, Model reduction of variable-geometry interconnects using variational spectrally-weighted balanced truncation, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Kanak Agarwal , Dennis Sylvester , David Blaauw , Frank Liu , Sani Nassif , Sarma Vrudhula, Variational delay metrics for interconnect timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Janet M. Wang , Omar A. Hafiz , Jun Li, A linear fractional transform (LFT) based model for interconnect parametric uncertainty, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Guoyong Shi , C.-J. Richard Shi, Parametric reduced order modeling for interconnect analysis, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.774-779, January 27-30, 2004, Yokohama, Japan
	Lou Scheffer, Explicit computation of performance as a function of process variation, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
	James D. Ma , Rob A. Rutenbar, Fast interval-valued statistical interconnect modeling and reduction, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Andrew B. Kahng , Bao Liu , Xu Xu, Statistical crosstalk aggressor alignment aware interconnect delay calculation, Proceedings of the international workshop on System-level interconnect prediction, March 04-05, 2006, Munich, Germany
	Kin Cheong Sou , Alexandre Megretski , Luca Daniel, A quasi-convex optimization approach to parameterized model order reduction, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Soroush Abbaspour , Hanif Fatemi , Massoud Pedram, Parameterized block-based non-gaussian statistical gate timing analysis, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Frank Liu, A practical method to estimate interconnect responses to variabilities, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Dian Zhou , Rui-Ming Li, Design and verification of high-speed VLSI physical design, Journal of Computer Science and Technology, v.20 n.2, p.147-165, March 2005
	Andrew B. Kahng , Bao Liu , Xu Xu, Statistical gate delay calculation with crosstalk alignment consideration, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Zhuo Feng , Peng Li, Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Zhenhai Zhu , Joel Phillips, Random sampling of moment graph: a stochastic Krylov-reduction algorithm, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Jeffrey Fan , Ning Mi , Sheldon X.-D. Tan , Yici Cai , Xianlong Hong, Statistical model order reduction for interconnect circuits considering spatial correlations, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	J. R. Phillips, Variational interconnect analysis via PMTBR, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.872-879, November 07-11, 2004
	J. Wang , P. Ghanta , S. Vrudhula, Stochastic analysis of interconnect performance in the presence of process variations, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.880-886, November 07-11, 2004
	J. D. Ma , R. A. Rutenbar, Interval-valued reduced order statistical interconnect modeling, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.460-467, November 07-11, 2004
	B. Bond , L. Daniel, Parameterized model order reduction of nonlinear dynamical systems, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.487-494, November 06-10, 2005, San Jose, CA
	Xin Li , Peng Li , L. T. Pileggi, Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.806-812, November 06-10, 2005, San Jose, CA
	Praveen Ghanta , Sarma Vrudhula, Variational Interconnect Delay Metrics for Statistical Timing Analysis, Proceedings of the 7th International Symposium on Quality Electronic Design, p.19-24, March 27-29, 2006
	Peng Li , Frank Liu , Xin Li , Lawrence T. Pileggi , Sani R. Nassif, Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction, Proceedings of the conference on Design, Automation and Test in Europe, p.958-963, March 07-11, 2005
	Yung-Ta Li , Zhaojun Bai , Yangfeng Su , Xuan Zeng, Parameterized model order reduction via a two-directional Arnoldi process, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Ruilin Wang , Cheng-Kok Koh, A frequency-domain technique for statistical timing analysis of clock meshes, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	J. V. R. Ravindra , M. B. Srinivas, Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs, Proceedings of the 2nd international conference on Nano-Networks, September 24-26, 2007, Catania, Italy
	Zeng Jun-Kuei , Chen Chung-Ping, Deep submicron interconnect timing model with quadratic random variable analysis, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Xiaoji Ye , Frank Liu , Peng Li, Fast variational interconnect delay and slew computation using quadratic models, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.8, p.913-926, August 2007
	Duo Li , Sheldon X.-D. Tan , Gengsheng Chen , Xuan Zeng, Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan