| High-level test generation for design verification of pipelined microprocessors |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
table of contents
New Orleans, Louisiana, United States
Pages: 185 - 188
Year of Publication: 1999
ISBN:1-58133-109-7
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Authors
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David Van Campenhout
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Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MI
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Trevor Mudge
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Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MI
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John P. Hayes
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Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MI
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Downloads (6 Weeks): 6, Downloads (12 Months): 19, Citation Count: 15
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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M.S. Abadir, J. Ferguson, and T. E. Kirkland. "Logic design verification via test generation." IEEE TCAD, vol. 7, no. 1, pp. 138-148, Jan. 1988.
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M. Abramovici. Digital systems testing and testable design. Computer Science Press, New York, 1990.
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3
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A. Aharon , B. Dorfman , E. Gofman , M. Leibowitz , V. Schwartzburd , A. Bar-David, Verification of the IBM RISC System/6000 by a dynamic biased pseudo-random test program generator, IBM Systems Journal, v.30 n.4, p.527-538, 1991
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5
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6
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7
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D. Bhattacharya and J. P. Hayes. "High-level test generation using bus faults." In Dig. FTCS, 1985, pp. 65-70.
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A. Chandra , V. Iyengar , D. Jameson , R. Jawalekar , I. Nair , B. Rosen , M. Mullen , J. Yoon , R. Armoni , D. Geist , Y. Wolfsthal, AVPGEN—a test generator for architecture verification, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.2, p.188-200, June 1995
[doi> 10.1109/92.386220]
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Farzan Fallah , Srinivas Devadas , Kurt Keutzer, OCCOM: efficient computation of observability-based code coverage metrics for functional verification, Proceedings of the 35th annual conference on Design automation, p.152-157, June 15-19, 1998, San Francisco, California, United States
[doi> 10.1145/277044.277078]
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Aarti Gupta , Sharad Malik , Pranav Ashar, Toward formalizing a validation methodology using simulation coverage, Proceedings of the 34th annual conference on Design automation, p.740-745, June 09-13, 1997, Anaheim, California, United States
[doi> 10.1145/266021.266359]
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Anoosh Hosseini , Dimitrios Mavroidis , Pavlos Konas, Code generation and analysis for the functional verification of micro processors, Proceedings of the 33rd annual conference on Design automation, p.305-310, June 03-07, 1996, Las Vegas, Nevada, United States
[doi> 10.1145/240518.240574]
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Hiroaki Iwashita , Satoshi Kowatari , Tsuneo Nakata , Fumiyasu Hirose, Automatic test program generation for pipelined processors, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.580-583, November 06-10, 1994, San Jose, California, United States
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J. Lee and J. H. Patel. "Architectural level test generation for microprocessors." IEEE TCAD, pp. 1288-1300, 1994.
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Scott Taylor , Michael Quinn , Darren Brown , Nathan Dohm , Scot Hildebrandt , James Huggins , Carl Ramey, Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor—the DEC Alpha 21264 microprocessor, Proceedings of the 35th annual conference on Design automation, p.638-643, June 15-19, 1998, San Francisco, California, United States
[doi> 10.1145/277044.277208]
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CITED BY 15
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Allon Adir , Hezi Azatchi , Eyal Bin , Ofer Peled , Kirill Shoikhet, A generic micro-architectural test plan approach for microprocessor verification, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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