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High-level test generation for design verification of pipelined microprocessors
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents
New Orleans, Louisiana, United States
Pages: 185 - 188  
Year of Publication: 1999
ISBN:1-58133-109-7
Authors
David Van Campenhout  Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MI
Trevor Mudge  Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MI
John P. Hayes  Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MI
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 6,   Downloads (12 Months): 19,   Citation Count: 15
Additional Information:

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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M.S. Abadir, J. Ferguson, and T. E. Kirkland. "Logic design verification via test generation." IEEE TCAD, vol. 7, no. 1, pp. 138-148, Jan. 1988.
 
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M. Abramovici. Digital systems testing and testable design. Computer Science Press, New York, 1990.
 
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D. Bhattacharya and J. P. Hayes. "High-level test generation using bus faults." In Dig. FTCS, 1985, pp. 65-70.
 
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J. Lee and J. H. Patel. "Architectural level test generation for microprocessors." IEEE TCAD, pp. 1288-1300, 1994.
 
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CITED BY  15

Collaborative Colleagues:
David Van Campenhout: colleagues
Trevor Mudge: colleagues
John P. Hayes: colleagues