Micro architecture coverage directed generation of test programs

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Micro architecture coverage directed generation of test programs

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 175 - 180

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Shmuel Ur	IBM Haifa Research Lab
Yaov Yadin	IBM Haifa Research Lab

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 23, Citation Count: 15

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	3	E. Buchnik , S. Ur, Compacting regression-suites on-the-fly, Proceedings of the Fourth Asia-Pacific Software Engineering and International Computer Science Conference, p.385, December 02-05, 1997
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	7	Daniel Geist , Monica Farkas , Avner Landver , Yossi Lichtenstein , Shmuel Ur , Yaron Wolfsthal, Coverage-Directed Test Generation Using Symbolic Techniques, Proceedings of the First International Conference on Formal Methods in Computer-Aided Design, p.143-158, November 06-08, 1996
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	13	Hiroaki Iwashita , Satoshi Kowatari , Tsuneo Nakata , Fumiyasu Hirose, Automatic test program generation for pipelined processors, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.580-583, November 06-10, 1994, San Jose, California, United States
	14	Ilan Beer , Shoham Ben-David , Daniel Geist , Raanan Gewirtzman , Michael Yoeli, Methodology and System for Practical Formal Verification of Reactive Hardware, Proceedings of the 6th International Conference on Computer Aided Verification, p.182-193, June 21-23, 1994
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	18	Daniel Lewin , Dean Lorenz , Shmuel Ur, A Methodology for Processor Implementation Verification, Proceedings of the First International Conference on Formal Methods in Computer-Aided Design, p.126-142, November 06-08, 1996
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CITED BY 15

	Shai Fine , Avi Ziv, Coverage directed test generation for functional verification using bayesian networks, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Hemant Rotithor, Postsilicon Validation Methodology for Microprocessors, IEEE Design & Test, v.17 n.4, p.77-88, October 2000
	Alon Gluska, Coverage-oriented verification of banias, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Young-Su Kwon , Young-Il Kim , Chong-Min Kyung, Systematic functional coverage metric synthesis from hierarchical temporal event relation graph, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Allon Adir , Hezi Azatchi , Eyal Bin , Ofer Peled , Kirill Shoikhet, A generic micro-architectural test plan approach for microprocessor verification, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Serdar Tasiran , Kurt Keutzer, Coverage Metrics for Functional Validation of Hardware Designs, IEEE Design & Test, v.18 n.4, p.36-45, July 2001
	Shai Fine , Yishay Mansour, Active sampling for multiple output identification, Machine Learning, v.69 n.2-3, p.213-228, December 2007
	Heon-Mo Koo , Prabhat Mishra, Test generation using SAT-based bounded model checking for validation of pipelined processors, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Heon-Mo Koo , Prabhat Mishra, Functional test generation using property decompositions for validation of pipelined processors, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Deepak A. Mathaikutty , Sandeep K. Shukla , Sreekumar V. Kodakara , David Lilja , Ajit Dingankar, Design fault directed test generation for microprocessor validation, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Qiang Zhu , Aviral Shrivastava , Nikil Dutt, Interactive presentation: Functional and timing validation of partially bypassed processor pipelines, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Prabhat Mishra , Nikil Dutt, Functional Coverage Driven Test Generation for Validation of Pipelined Processors, Proceedings of the conference on Design, Automation and Test in Europe, p.678-683, March 07-11, 2005
	Prabhat Mishra , Nikil Dutt, Graph-Based Functional Test Program Generation for Pipelined Processors, Proceedings of the conference on Design, automation and test in Europe, p.10182, February 16-20, 2004
	Prabhat Mishra , Nikil Dutt, Specification-driven directed test generation for validation of pipelined processors, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.3, p.1-36, July 2008
	Heon-Mo Koo , Prabhat Mishra, Functional test generation using design and property decomposition techniques, ACM Transactions on Embedded Computing Systems (TECS), v.8 n.4, p.1-33, July 2009