| Memory exploration for low power, embedded systems |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
table of contents
New Orleans, Louisiana, United States
Pages: 140 - 145
Year of Publication: 1999
ISBN:1-58133-109-7
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Authors
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Wen-Tsong Shiue
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Arizona State University, Department of Electrical Engineering, Tempe, AZ
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Chaitali Chakrabarti
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Arizona State University, Department of Electrical Engineering, Tempe, AZ
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| Bibliometrics |
Downloads (6 Weeks): 4, Downloads (12 Months): 26, Citation Count: 57
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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P. R. Panda, N. D. Dutt, and A. Nicolau. "Data Cache Sizing for Embedded Processor Applications." Technical Report ICS-TR-97-31, University of California, Irvine, June 1997.
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S. E. Wilton and N. Jouppi, "An Enhanced Access and Cycle Time Model for On-chip Caches", Digital Equipment Corporation Western Research Lab, Tech. Report 93/5, 1994.
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Patrick Hicks , Matthew Walnock , Robert Michael Owens, Analysis of power consumption in memory hierarchies, Proceedings of the 1997 international symposium on Low power electronics and design, p.239-242, August 18-20, 1997, Monterey, California, United States
[doi> 10.1145/263272.263342]
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A. Thordarson, "Comparison of Manual and Automatic Behavioral Synthesis of MPEG Algorithm", Master' s thesis, University of California, Irvine, 1995.
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Darko Kirovski , Chunho Lee , Miodrag Potkonjak , William Mangione-Smith, Application-driven synthesis of core-based systems, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.104-107, November 09-13, 1997, San Jose, California, United States
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J. Edler and M. D. Hill, " Dinero IV Trace-Driven Uniprocessor Cache Simulator", web site: http://www.neci.nj.nec.com/homepages/edler/d4 or http://www.cs.wisc.edu/Nmarkhill/DineroIV.
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CITED BY 57
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P. R. Panda , F. Catthoor , N. D. Dutt , K. Danckaert , E. Brockmeyer , C. Kulkarni , A. Vandercappelle , P. G. Kjeldsberg, Data and memory optimization techniques for embedded systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.2, p.149-206, April 2001
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M. Kandemir , J. Ramanujam , J. Irwin , N. Vijaykrishnan , I. Kadayif , A. Parikh, Dynamic management of scratch-pad memory space, Proceedings of the 38th conference on Design automation, p.690-695, June 2001, Las Vegas, Nevada, United States
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Takanori Okuma , Yun Cao , Masanori Muroyama , Hiroto Yasuura, Reducing access energy of on-chip data memory considering active data bitwidth, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
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M. Kandemir , N. Vijaykrishnan , M. J. Irwin , W. Ye, Influence of compiler optimizations on system power, Proceedings of the 37th conference on Design automation, p.304-307, June 05-09, 2000, Los Angeles, California, United States
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Federico Angiolini , Luca Benini , Alberto Caprara, Polynomial-time algorithm for on-chip scratchpad memory partitioning, Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, October 30-November 01, 2003, San Jose, California, USA
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L. Benini , L. Macchiarulo , A. Macii , E. Macii , M. Poncino, From architecture to layout: partitioned memory synthesis for embedded systems-on-chip, Proceedings of the 38th conference on Design automation, p.784-789, June 2001, Las Vegas, Nevada, United States
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Federico Angiolini , Francesco Menichelli , Alberto Ferrero , Luca Benini , Mauro Olivieri, A post-compiler approach to scratchpad mapping of code, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
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Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau , Francky Catthoor , Arnout Vandecappelle , Erik Brockmeyer , Chidamber Kulkarni , Eddy De Greef, Data Memory Organization and Optimizations in Application-Specific Systems, IEEE Design & Test, v.18 n.3, p.56-68, May 2001
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M. Kandemir , O. Ozturk , M. Karakoy, Dynamic on-chip memory management for chip multiprocessors, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
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Murali Jayapala , Francisco Barat , Tom Vander Aa , Francky Catthoor , Henk Corporaal , Geert Deconinck, Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors, IEEE Transactions on Computers, v.54 n.6, p.672-683, June 2005
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Ismail Kadayif , Mahmut Kandemir , Guilin Chen , Ozcan Ozturk , Mustafa Karakoy , Ugur Sezer, Optimizing Array-Intensive Applications for On-Chip Multiprocessors, IEEE Transactions on Parallel and Distributed Systems, v.16 n.5, p.396-411, May 2005
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Olga Golubeva , Mirko Loghi , Massimo Poncino , Enrico Macii, Architectural leakage-aware management of partitioned scratchpad memories, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
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