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Memory exploration for low power, embedded systems
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents
New Orleans, Louisiana, United States
Pages: 140 - 145  
Year of Publication: 1999
ISBN:1-58133-109-7
Authors
Wen-Tsong Shiue  Arizona State University, Department of Electrical Engineering, Tempe, AZ
Chaitali Chakrabarti  Arizona State University, Department of Electrical Engineering, Tempe, AZ
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 26,   Citation Count: 57
Additional Information:

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
P. R. Panda, N. D. Dutt, and A. Nicolau. "Data Cache Sizing for Embedded Processor Applications." Technical Report ICS-TR-97-31, University of California, Irvine, June 1997.
 
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S. E. Wilton and N. Jouppi, "An Enhanced Access and Cycle Time Model for On-chip Caches", Digital Equipment Corporation Western Research Lab, Tech. Report 93/5, 1994.
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A. Thordarson, "Comparison of Manual and Automatic Behavioral Synthesis of MPEG Algorithm", Master' s thesis, University of California, Irvine, 1995.
 
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11
J. Edler and M. D. Hill, " Dinero IV Trace-Driven Uniprocessor Cache Simulator", web site: http://www.neci.nj.nec.com/homepages/edler/d4 or http://www.cs.wisc.edu/Nmarkhill/DineroIV.

CITED BY  57

Collaborative Colleagues:
Wen-Tsong Shiue: colleagues
Chaitali Chakrabarti: colleagues