A low power hardware/software partitioning approach for core-based embedded systems

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A low power hardware/software partitioning approach for core-based embedded systems

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 122 - 127

Year of Publication: 1999

ISBN:1-58133-109-7

Author

Jörg Henkel

C&C Research Laboratories, NEC, 4 Independence Way, Princeton, NJ

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 41, Citation Count: 35

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 35

	Marcello Lajolo , Anand Raghunathan , Sujit Dey, Efficient power co-estimation techniques for system-on-chip design, Proceedings of the conference on Design, automation and test in Europe, p.27-34, March 27-30, 2000, Paris, France
	Frank Vahid, Partitioning sequential programs for CAD using a three-step approach, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.3, p.413-429, July 2002
	Luca Benini , Giovanni De Micheli, System-level power optimization: techniques and tools, Proceedings of the 1999 international symposium on Low power electronics and design, p.288-293, August 16-17, 1999, San Diego, California, United States
	A. Doboli, Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints, Proceedings of the conference on Design, automation and test in Europe, p.612-619, March 2001, Munich, Germany
	Marcello Lajolo , Anand Raghunathan , Sujit Dey , Luciano Lavagno, Cosimulation-based power estimation for system-on-chip design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.253-266, June 2002
	Niraj K. Jha, Low power system scheduling and synthesis, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Greg Stitt , Roman Lysecky , Frank Vahid, Dynamic hardware/software partitioning: a first approach, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Greg Stitt , Frank Vahid, Hardware/software partitioning of software binaries, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.164-170, November 10-14, 2002, San Jose, California
	Greg Stitt , Frank Vahid , Shawn Nematbakhsh, Energy savings and speedups from partitioning critical software loops to hardware in embedded systems, ACM Transactions on Embedded Computing Systems (TECS), v.3 n.1, p.218-232, February 2004
	N. Julien , S. Gailhard , E. Martin, Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT, Journal of VLSI Signal Processing Systems, v.35 n.2, p.195-211, September 2003
	Greg Stitt , Frank Vahid, Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic, IEEE Design & Test, v.19 n.6, p.36-43, November 2002
	Brian Grattan , Greg Stitt , Frank Vahid, Codesign-extended applications, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
	Nattawut Thepayasuwan , Alex Doboli, Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.5, p.525-538, May 2005
	Antonio Carlos S. Beck , Luigi Carro, Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Greg Stitt , Frank Vahid , Gordon McGregor , Brian Einloth, Hardware/software partitioning of software binaries: a case study of H.264 decode, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
	M. Finc , A. Zemva, Profiling soft-core processor applications for hardware/software partitioning, Journal of Systems Architecture: the EUROMICRO Journal, v.51 n.5, p.315-329, May 2005
	Michalis D. Galanis , Gregory Dimitroulakos , Costas E. Goutis, Performance improvements from partitioning applications to FPGA hardware in embedded SoCs, The Journal of Supercomputing, v.35 n.2, p.185-199, February 2006
	Greg Stitt, Hardware/software partitioning with multi-version implementation exploration, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
	Scott Sirowy , Greg Stitt , Frank Vahid, C is for circuits: capturing FPGA circuits as sequential code for portability, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
	Michalis D. Galanis , Gregory Dimitroulakos , Costas E. Goutis, A partitioning flow for accelerating applications in processor-FPGA systems, Proceedings of the 9th WSEAS International Conference on Computers, p.1-6, July 14-16, 2005, Athens, Greece
	Yun Cao , Hiroto Yasuura, A system-level energy minimization approach using datapath width optimization, Proceedings of the 2001 international symposium on Low power electronics and design, p.231-236, August 2001, Huntington Beach, California, United States
	Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000
	M. D. Galanis , A. Milidonis , G. Theodoridis , D. Soudris , C. E. Goutis, Automated framework for partitioning DSP applications in hybrid reconfigurable platforms, Microprocessors & Microsystems, v.31 n.1, p.1-14, February, 2007
	Michalis D. Galanis , Gregory Dimitroulakos , Costas E. Goutis, Partitioning Methodology for Heterogeneous Reconfigurable Functional Units, The Journal of Supercomputing, v.38 n.1, p.17-34, October 2006
	Roman Lysecky, Low-power warp processor for power efficient high-performance embedded systems, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Scott Sirowy , Yonghui Wu , Stefano Lonardi , Frank Vahid, Two-level microprocessor-accelerator partitioning, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Madhura Purnaprajna , Marek Reformat , Witold Pedrycz, Genetic algorithms for hardware-software partitioning and optimal resource allocation, Journal of Systems Architecture: the EUROMICRO Journal, v.53 n.7, p.339-354, July, 2007
	Roman Lysecky , Frank Vahid, A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning, Proceedings of the conference on Design, Automation and Test in Europe, p.18-23, March 07-11, 2005
	Greg Stitt , Frank Vahid, A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms, Proceedings of the conference on Design, Automation and Test in Europe, p.396-397, March 07-11, 2005
	Roman Lysecky , Frank Vahid, A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning, Proceedings of the conference on Design, automation and test in Europe, p.10480, February 16-20, 2004
	Lance Saldanha , Roman Lysecky, Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits, Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, October 19-24, 2008, Atlanta, GA, USA
	Hamid Noori , Farhad Mehdipour , Koji Inoue , Kazuaki Murakami, Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
	Jigang Wu , Thambipillai Srikanthan , Chengbin Yan, Algorithmic aspects for power-efficient hardware/software partitioning, Mathematics and Computers in Simulation, v.79 n.4, p.1204-1215, December, 2008
	Roman Lysecky, Scalability and parallel execution of warp processing: dynamic hardware/software partitioning, International Journal of Parallel Programming, v.36 n.5, p.478-492, October 2008
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