Automatic synthesis and optimization of partially specified asynchronous systems

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Automatic synthesis and optimization of partially specified asynchronous systems

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 110 - 115

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Alex Kondratyev	Univ. of Aizu, Japan
Jordi Cortadella	Univ. Politècnica, Catalunya, Spain
Michael Kishinevsky	Intel Corp.
Luciano Lavagno	Univ. of Udine, Italy
Alexander Yakovlev	Univ. of Newcastle, upon Tyne, UK

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 6, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Kees van Berkel, Handshake circuits: an asynchronous architecture for VLSI programming, Cambridge University Press, New York, NY, 1993
	2	T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications. PhD thesis, MIT, June 1987.
	3	J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev. Automatic handshake expansion and reshuffling using concurrency reduction. In Workshop on Hardware Design and Petri Nets, pages 86-110, June 1998.
	4	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alex Yakovlev. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Transactions on Information and Systems, ES0-D(3):315-325, 1997.
	5	Bill Lin , Chantal Ykman-Couvreur , Peter Vanbekbergen, A general state graph transformation framework for asynchronous synthesis, Proceedings of the conference on European design automation, p.448-453, September 19-23, 1994, Grenoble, France
	6	Alain J. Martin. Synthesis of asynchronous VLSI circuits. In J. Straunstrup, editor, Formal Methods for VLSI Design, chapter 6, pages 237- 283. North-Holland, 1990.
	7	T. Murata. Petri Nets: Properties, analysis and applications. Proceedings of the IEEE, pages 541-580, April 1989.
	8	Chris J. Myers and Teresa H.-Y. Meng. Synthesis of timed asynchronous circuits. IEEE Transactions on VLSI Systems, 1(2):106-119, June 1993.
	9	Ad Peeters. Implementation of a parallel component in tangram. Personal communication, 1997.

CITED BY 2

	Jordi Cortadella , Michael Kishinevsky , Steven M. Burns , Ken Stevens, Synthesis of asynchronous control circuits with automatically generated relative timing assumptions, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.324-331, November 07-11, 1999, San Jose, California, United States
	Peggy B. McGee , Steven M. Nowick, A lattice-based framework for the classification and design of asynchronous pipelines, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA