Crosstalk minimization using wire perturbations

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Crosstalk minimization using wire perturbations

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 100 - 103

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Prashant Saxena	Strategic CAD Labs, Intel Corporation, Hillsboro, OR
C. L. Liu	Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 14, Citation Count: 9

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Bakoglu, H. B., Circuits, Interconnections and Packaging for VLSI, Addison-Wesley Publishing Company, 1990.
	2	Kamal Chaudhary , Akira Onozawa , Ernest S. Kuh, A spacing algorithm for performance enhancement and cross-talk reduction, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.697-702, November 07-11, 1993, Santa Clara, California, United States
	3	David N. Deutsch, A “Dogleg” channel router, Proceedings of the 13th conference on Design automation, p.425-433, June 28-30, 1976, San Francisco, California, United States [doi>10.1145/800146.804843]
	4	Gao, T. and C. L. Liu, "Minimum Crosstalk Channel Routing", IEEE Trans. Computer-Aided Design 15 (5), 465-474, 1996.
	5	Hall, H. S. and S. R. Knight, Higher Algebra, Macmillan & Co. Ltd., London, 4fh ed., 1891. Reprinted, 1960.
	6	Karnik, T., Intel Corp., Hillsboro, OR, Private communication, 1997.
	7	H. W. Leong , C. L. Liu, A new channel routing problem, Proceedings of the 20th conference on Design automation, p.584-590, June 27-29, 1983, Miami Beach, Florida, United States
	8	Sakurai, T. and K. Tamaru, "Simple Formulas for Two- and Three- Dimensional Capacitances", IEEE Trans. Electron Devices ED-30 (2), 183-185, 1983.
	9	Prashant Saxena, The retiming and routing of VLSI circuits, University of Illinois at Urbana-Champaign, Champaign, IL, 1998
	10	Wong, D. F. and C. L. Liu, "Compacted Channel Routing with Via Placement Restriction", Integration 4 (4), 267-307, 1986.
	11	Yoshimura, T. and E. S. Kuh, "Efficient Algorithms for Channel Routing", IEEE Trans. Computer-Aided Design CAD-1 (1), 25-35, 1982.

CITED BY 9

	Ki-Wook Kim , Unni Narayanan , Sung-Mo Kang, Domino logic synthesis minimizing crosstalk, Proceedings of the 37th conference on Design automation, p.280-285, June 05-09, 2000, Los Angeles, California, United States
	Iris Hui-Ru Jiang , Song-Ra Pan , Yao-Wen Chang , Jing-Yang Jou, Optimal reliable crosstalk-driven interconnect optimization, Proceedings of the 2000 international symposium on Physical design, p.128-133, May 2000, San Diego, California, United States
	Rony Kay , Rob A. Rutenbar, Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution, Proceedings of the 2000 international symposium on Physical design, p.61-68, May 2000, San Diego, California, United States
	Ki-Wook Kim , Seong-Ook Jung , Unni Narayanan , C. L. Liu , Sung-Mo Kang, Noise-aware interconnect power optimization in domino logic synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.79-89, February 2003
	Paul B. Morton , Wayne Dai, Crosstalk noise estimation for noise management, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Murat R. Becer , David Blaauw , Ilan Algor , Rajendran Panda , Chanhee Oh , Vladimir Zolotov , Ibrahim N. Hajj, Post-route gate sizing for crosstalk noise reduction, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Masanori Hashimoto , Masao Takahashi , Hidetoshi Onodera, Crosstalk noise optimization by post-layout transistor sizing, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Murat Becer , Ravi Vaidyanathan , Chanhee Oh , Rajendran Panda, Signal integrity management in an SoC physical design flow, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Iris Hui-Ru Jiang , Song-Ra Pan , Yao-Wen Chang , Jing-Yang Jou, Reliable crosstalk-driven interconnect optimization, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.1, p.88-103, January 2006