Simultaneous routing and buffer insertion with restrictions on buffer locations

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Simultaneous routing and buffer insertion with restrictions on buffer locations

Full text

Pdf (673 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 96 - 99

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Hai Zhou	Department of Computer Sciences, University of Texas, Austin, TX
D. F. Wong	Department of Computer Sciences, University of Texas, Austin, TX
I-Min Liu	Department of Electrical and Computer Engineering, University of Texas, Austin, TX
Adnan Aziz	Department of Electrical and Computer Engineering, University of Texas, Austin, TX

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 11, Citation Count: 25

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/309847.309885 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Semiconductor Industry Association. National technology roadmap for semiconductors, 1994.
	2	H. B. Bakoglu. Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, 1990.
	3	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
	4	E. W. Dijkstra. A note on two problems in connection with graphs. Numerische Math., 1:269-271, 1959.
	5	W. C. Elmore. The transient response of dampled linear networks with particular regard to wide-band amplifiers. Journal of Applied Physics, 19(1):55-63, January 1948.
	6	M. R. Garey and D. S. Johnson. Computers and Intractability. W. H. Freeman and Co., 1979.
	7	Lalgudi N. Kannan , Peter R. Suaris , Hong-Gee Fang, A methodology and algorithms for post-placement delay optimization, Proceedings of the 31st annual conference on Design automation, p.327-332, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196399]
	8	J. Lillis, C. K. Cheng, and T. T. Lin. Optimal and efficient buffer insertion and wire sizing. In CICC, pages 259-262, 1995.
	9	Takumi Okamoto , Jason Cong, Buffered Steiner tree construction with wire sizing for interconnect layout optimization, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.44-49, November 10-14, 1996, San Jose, California, United States
	10	Amir H. Salek , Jinan Lou , Massoud Pedram, A simultaneous routing tree construction and fanout optimization algorithm, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.625-630, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.289098]
	11	L. P. P. P. van Ginneken. Buffer placement in distributed RC-tree networks for minimal Elmore delay. In IS CA S, pages 865-868, 1990.

CITED BY 25

	Charles Alpert , Chris Chu , Gopal Gandham , Miloš Hrkić , Jiang Hu , Chandramouli Kashyap , Stephen Quay, Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Ashok Jagannathan , Sung-Woo Hur , John Lillis, A fast algorithm for context-aware buffer insertion, Proceedings of the 37th conference on Design automation, p.368-373, June 05-09, 2000, Los Angeles, California, United States
	I-Min Liu , Adnan Aziz , D. F. Wong, Meeting delay constraints in DSM by minimal repeater insertion, Proceedings of the conference on Design, automation and test in Europe, p.436-440, March 27-30, 2000, Paris, France
	Ashok Jagannathan , Sung-Woo Hur , John Lillis, A fast algorithm for context-aware buffer insertion, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.1, p.173-188, January 2002
	Olivier Coudert, Logical and physical design: a flow perspective, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Jason Cong , Xin Yuan, Routing tree construction under fixed buffer locations, Proceedings of the 37th conference on Design automation, p.379-384, June 05-09, 2000, Los Angeles, California, United States
	Minghorng Lai , D. F. Wong, Maze routing with buffer insertion and wiresizing, Proceedings of the 37th conference on Design automation, p.374-378, June 05-09, 2000, Los Angeles, California, United States
	Miloš Hrkić , John Lillis, Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Olivier Coudert , Jason Cong , Sharad Malik , Majid Sarrafzadeh, Incremental CAD, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Charles J. Alpert , Gopal Gandham , Miloš Hrkić , Jiang Hu , Stephen T. Quay, Porosity aware buffered steiner tree construction, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Xiaoping Tang , Martin D. F. Wong, Tradeoff routing resource, runtime and quality in buffered routing, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.430-433, January 27-30, 2004, Yokohama, Japan
	Sampath Dechu , Zion Cien Shen , Chris C. N. Chu, An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.361-366, January 27-30, 2004, Yokohama, Japan
	C. N. Sze , Jiang Hu , Charles J. Alpert, A place and route aware buffered Steiner tree construction, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.355-360, January 27-30, 2004, Yokohama, Japan
	Jiang Hu , Charles J. Alpert , Stephen T. Quay , Gopal Gandham, Buffer insertion with adaptive blockage avoidance, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Charles J. Alpert , Miloš Hrkić , Jiang Hu , Stephen T. Quay, Fast and flexible buffer trees that navigate the physical layout environment, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Miloš Hrkić , John Lillis, S-Tree: a technique for buffered routing tree synthesis, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Xiaoping Tang , Ruiqi Tian , Hua Xiang , D. F. Wong, A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Zhong-Ching Lu , Ting-Chi Wang, Concurrent flip-flop and buffer insertion with adaptive blockage avoidance, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Xiaoping Tang , D. F. Wong, Planning buffer locations by network flows, Proceedings of the 2000 international symposium on Physical design, p.180-185, May 2000, San Diego, California, United States
	Chuan Lin , Hai Zhou, Optimal wire retiming without binary search, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.452-458, November 07-11, 2004
	Ruiming Chen , Hai Zhou, Efficient algorithms for buffer insertion in general circuits based on network flow, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.322-326, November 06-10, 2005, San Jose, CA
	Chuan Lin , Hai Zhou, Retiming for Wire Pipelining in System-On-Chip, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.215, November 09-13, 2003
	Wei Chen , Massoud Pedram , Premal Buch, Buffered Routing Tree Construction Under Buffer Placement Blockages, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.381, January 07-11, 2002
	Chuan Lin , Hai Zhou, Wire Retiming for System-on-Chip by Fixpoint Computation, Proceedings of the conference on Design, automation and test in Europe, p.21092, February 16-20, 2004
	Ruiming Chen , Hai Zhou, Fast min-cost buffer insertion under process variations, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California