Common-case computation

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Common-case computation: a high-level technique for power and performance optimization

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 56 - 61

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Ganesh Lakshminarayana	CCRL-NEC, Princeton University
Anand Raghunathan	CCRL-NEC, Princeton University
Kamal S. Khouri	Dept. of Electrical Engg., Princeton University
Niraj K. Jha	Dept. of Electrical Engg., Princeton University
Sujit Dey	Dept. of Electrical Engg., Univ. of California, San Diego

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 14, Citation Count: 16

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	8	Anand Raghunathan , Niraj K. Jha , Sujit Dey, High-Level Power Analysis and Optimization, Kluwer Academic Publishers, Norwell, MA, 1998
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	14	Ganesh Lakshminarayana , Niraj K. Jha, FACT: a framework for the application of throughput and power optimizing transformations to control-flow intensive behavioral descriptions, Proceedings of the 35th annual conference on Design automation, p.102-107, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277066]
	15	OpenCAD V 5 Users Manual, NEC Electronics, Inc., Sept. 1997.

CITED BY 16

	Alex Jones , Debabrata Bagchi , Sartajit Pal , Prith Banerjee , Alok Choudhary, PACT HDL: a compiler targeting ASICS and FPGAS with power and performance optimizations, Power aware computing, Kluwer Academic Publishers, Norwell, MA, 2002
	Weidong Wang , Anand Raghunathan , Ganesh Lakshminarayana , Niraj K. Jha, Input space adaptive design: a high-level methodology for energy and performance optimization, Proceedings of the 38th conference on Design automation, p.738-743, June 2001, Las Vegas, Nevada, United States
	Alex Jones , Debabrata Bagchi , Satrajit Pal , Xiaoyong Tang , Alok Choudhary , Prith Banerjee, PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
	Luca Benini , Giovanni De Micheli, Logic synthesis for low power, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Massoud Pedram, Power optimization and management in embedded systems, Proceedings of the 2001 conference on Asia South Pacific design automation, p.239-244, January 2001, Yokohama, Japan
	Eui-Young Chung , Luca Benini , Giovanni De Micheli, Automatic source code specialization for energy reduction, Proceedings of the 2001 international symposium on Low power electronics and design, p.80-83, August 2001, Huntington Beach, California, United States
	Luca Benini , Alberto Macii , Enrico Macii , Elvira Omerbegovic , Fabrizio Pro , Massimo Poncino, Energy-aware design techniques for differential power analysis protection, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Tony Givargis , Frank Vahid , Jörg Henkel, A hybrid approach for core-based system-level power modeling, Proceedings of the 2000 conference on Asia South Pacific design automation, p.141-146, January 2000, Yokohama, Japan
	Weidong Wang , Anand Raghunathan , Ganesh Lakshminarayana , Niraj K. Jha, Input space adaptive design: a high-level methodology for optimizing energy and performance, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.6, p.590-602, June 2004
	N. Julien , S. Gailhard , E. Martin, Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT, Journal of VLSI Signal Processing Systems, v.35 n.2, p.195-211, September 2003
	Roman Lysecky , Susan Cotterell , Frank Vahid, A fast on-chip profiler memory, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Pietro Babighian , Luca Benini , Enrico Macii, A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks, Proceedings of the conference on Design, automation and test in Europe, p.10500, February 16-20, 2004
	Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000
	M. Kandemir , I. Kolcu , W. Zhang, Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy, Proceedings of the conference on Design, Automation and Test in Europe, p.11058, March 03-07, 2003
	Ajay Nair , Roman Lysecky, Non-intrusive dynamic application profiler for detailed loop execution characterization, Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, October 19-24, 2008, Atlanta, GA, USA
	Yu-Min Kuo , Shih-Hung Weng , Shih-Chieh Chang, A novel sequential circuit optimization with clock gating logic, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California