Object-oriented reuse methodology for VHDL

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Object-oriented reuse methodology for VHDL

Full text

Pdf (146 KB)

Source

Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Article No. 133

Year of Publication: 1999

ISBN:1-58113-121-6

Authors

Cristina Barna	Forschungszentrum Informatik, Germany
Wolfgang Rosenstiel	Universität Tübingen, Tübingen, Germany

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 11, Citation Count: 4

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/307418.307590 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	[1] IEEE Standard VHDL Language Reference Manual. IEEE standard 1076-1993, 1993.
	2	P. J. Ashenden , P. A. Wilsey , D. E. Martin, SUAVE: Painless Extension For An Object-Oriented VHDL, Proceedings of the 1997 VHDL International User's Forum (VIUF '97), p.60, October 19-22, 1997
	3	Judith Benzakki , Bachir Djafri, Object oriented extensions to VHDL, the LaMI proposal, Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems, p.334-347, August 1997, Toledo, Spain
	4	[4] D. Cabanis and S. Medhat. Object-Oriented Extensions to VHDL: The Classification Orientation. In Proc. of the VHDL User Forum Europe 1996. Shaker Verlag, 1996.
	5	[5] P. Campbell, M. Vai, and Z. Navabi. Implementation of IEEE Std 1149.1-1990 in VHDL. Proc. of the VHDL International Users' Forum Conference, 1992.
	6	[6] D. Eisenbiegler and C. Blumenröhr. Gropius - Advanced Reuse Concepts in a New Hardware Description Language. Proc. of the 2nd GI/ITG/GMM Workshop Reuse Techniques for VLSI Design, 1998.
	7	[7] S. Maginot, W. Nebel, W. Putzke-Röming, and M. Radetzki. Final Objective VHDL Language Definition. Technical report, LEDA and OFFI, May 1997.
	8	W. Putzke-Röming , M. Radetzki , W. Nebel, A flexible message passing mechanism for objective VHDL, Proceedings of the conference on Design, automation and test in Europe, p.242-249, February 23-26, 1998, Le Palais des Congrés de Paris, France
	9	[9] A. Reutter, B. Mößner, I. Kreutzer, and W. Rosenstiel. Wiederverwendung komplexer Komponenten für Synthese und Simulation unter Verwendung von VHDL. In L. Peters and K. Lagemann, editors, Entwurf Integrierter Schaltungen, 8. E.I.S.-Workshop, Tagungsband, Apr. 1997.
	10	G. Schumacher , W. Nebel, Object-oriented modelling of parallel hardware systems, Proceedings of the conference on Design, automation and test in Europe, p.234-241, February 23-26, 1998, Le Palais des Congrés de Paris, France
	11	[11] R. Seepold. A Hardware Design Methodology with Special Emphasis on Reuse and Synthesis. PhD thesis, Univ. of Tübingen, 1997.

CITED BY 4

	James Smith , Giovanni De Micheli, Polynomial circuit models for component matching in high-level synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.783-800, 12/1/2001
	Andreas Vörg , Wolfgang Rosenstiel, Automation of IP qualification and IP exchange, Integration, the VLSI Journal, v.37 n.4, p.323-352, September 2004
	Flávio R. Wagner , Wander O. Cesário , Luigi Carro , Ahmed A. Jerraya, Strategies for the integration of hardware and software IP components in embedded systems-on-chip, Integration, the VLSI Journal, v.37 n.4, p.223-252, September 2004
	Flávio R. Wagner , Wander Cesário , Ahmed A. Jerraya, Hardware/software IP integration using the ROSES design environment, ACM Transactions on Embedded Computing Systems (TECS), v.6 n.3, p.17-es, July 2007