ATPG tools for delay faults at the functional level

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ATPG tools for delay faults at the functional level

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Article No. 124

Year of Publication: 1999

ISBN:1-58113-121-6

Authors

S. Tragoudas	Electrical and Computer Engineering Department, The University of Arizona, Tucson, AZ
M. Michael	Electrical and Computer Engineering Department, The University of Arizona, Tucson, AZ

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 6, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Prathima Agrawal , Debashis Bhattacharya , Vishwani D. Agrawal, Test Generation for Path Delay Faults Using Binary Decision Diagrams, IEEE Transactions on Computers, v.44 n.3, p.434-447, March 1995 [doi>10.1109/12.372035]
	2	Karl S. Brace , Richard L. Rudell , Randal E. Bryant, Efficient implementation of a BDD package, Proceedings of the 27th ACM/IEEE conference on Design automation, p.40-45, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123222]
	3	Randal E. Bryant, Graph-Based Algorithms for Boolean Function Manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, August 1986 [doi>10.1109/TC.1986.1676819]
	4	[4] J. Crawfort, NTAB:Propositional Satisfiability Checker, CIRL, The University of Oregon, 1996.
	5	[5] S. Devadas, K. Keutzer, S. Malik, A. Wang, "Computation of floating mode delay in combinational circuits: Practice and Implementation", IEEE Transactions on Computer-Aided-Design , 12(12):1924-1936, December 1993.
	6	Rolf Drechsler, BiTeS: a BDD based test pattern generator for strong robust path delay faults, Proceedings of the conference on European design automation, p.322-327, September 19-23, 1994, Grenoble, France
	7	[7] J. P. Marques Silva, K. A. Sakallah, "GRASP-A New Search Algorithm for Satisfiability", IEEE Transactions on Computers, 1996, pp. 220-227.
	8	[8] P. C. McGeer, A. Saldanha, R. K. Brayton, A. Sangiovanni-Vincentlli, "Delay models and exact timing analysis. In T. Sasao, editor Logic Synthesis and Optimization , pages 167-189, Kluwer Academic Publishers, 1993.
	9	Irith Pomeranz , Sudhakar M. Reddy, Functional test generation for delay faults in combinational circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.687-694, November 05-09, 1995, San Jose, California, United States
	10	Irith Pomeranz , Sudhakar M. Reddy, On testing delay faults in macro-based combinational circuits, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.332-339, November 06-10, 1994, San Jose, California, United States
	11	[11] F. Somenzi, CUDD:CU Decision Diagram Package, Release 2.2.0, Department of Electrical and Computer Engineering, The University of Colorado at Boulder, 1998.
	12	[12] S. Tragoudas, M. Michael, "ATPG Tools for Delay Faults at the Functional Level", Technical Report CENG-TR- 98-118, ECE Dept., The University of Arizona.
	13	Bill Underwood , Wai-On Law , Sungho Kang , Haluk Konuk, Fastpath: A Path-Delay Test Generator for Standard Scan Designs, Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years, p.154-163, October 02-06, 1994

CITED BY 2

	M. Michael , S. Tragoudas, ATPG tools for delay faults at the functional level, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.1, p.33-57, January 2002
	Jesse Whittemore , Joonyoung Kim , Karem Sakallah, SATIRE: a new incremental satisfiability engine, Proceedings of the 38th conference on Design automation, p.542-545, June 2001, Las Vegas, Nevada, United States