Post-placement residual-overlap removal with minimal movement

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Post-placement residual-overlap removal with minimal movement

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Article No. 116

Year of Publication: 1999

ISBN:1-58113-121-6

Authors

Sudip Nag	Xilinx Inc, San Jose, CA
Kamal Chaudhary	Xilinx Inc, San Jose, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 14, Citation Count: 9

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Hiroshi Murata , Kunihiro Fujiyoshi , Shigetoshi Nakatake , Yoji Kajitani, Rectangle-packing-based module placement, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.472-479, November 05-09, 1995, San Jose, California, United States
	2	[2] W.M. Dai and E.S. Kuh, "Simultaneous Floorplanning and Global Routing for Hierarchical Building Block Layout," IEEE Transactions on CAD, vol. CAD-6, no 5, pp. 828-837, Sept. 1987.
	3	D. F. Wong , C. L. Liu, A new algorithm for floorplan design, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.101-107, July 1986, Las Vegas, Nevada, United States
	4	[4] G. Vijayan and R.S. Tsay., "Floorplanning by Topological Constraint Reduction," Proc. of ICCAD 1990.
	5	J. Frankle, Iterative and adaptive slack allocation for performance-driven layout and FPGA routing, Proceedings of the 29th ACM/IEEE conference on Design automation, p.536-542, June 08-12, 1992, Anaheim, California, United States
	6	[6] H. Youssef and E. Shragowitz, "Timing constraints for correct performance," Proc. of ICCAD 1990.
	7	[7] C. Sechen and K.W. Lee, "An improved simulated-annealing algorithm for row-based placement," Proc. of ICCAD 1987.
	8	[8] J.M. Cohn, D.J. Garrod, R.A. Rutenbar and L.R. Carley, "KOAN/ANAGRAMII: New Tools for Device-Level Analog Placement and Routing", IEEE Journal of Solid State Circuits, 1991.
	9	[9] A. Srinivasan, K. Chaudhary, and E.S. Kuh, "RITUAL: A performance driven placement algorithm," IEEE Trans. CAS, Nov. 1992.
	10	[10] The Programmable Logic Data Book, Xilinx Inc., San Jose California, 1996.

CITED BY 9

	Hua Xiang , Kai-Yuan Chao , D. F. Wong, ECO algorithms for removing overlaps between power rails and signal wires, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.67-74, November 10-14, 2002, San Jose, California
	Stelian Alupoaei , Srinivas Katkoori, Ant colony system application to macrocell overlap removal, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.10, p.1118-1122, October 2004
	S. N. Adya , I. L. Markov, Combinatorial techniques for mixed-size placement, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.1, p.58-90, January 2005
	Jason Cong , Min Xie, A robust detailed placement for mixed-size IC designs, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Chin-Chih Chang , Jason Cong , Xin Yuan, Multi-level placement for large-scale mixed-size IC designs, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Michael D. Moffitt , Aaron N. Ng , Igor L. Markov , Martha E. Pollack, Constraint-driven floorplan repair, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Kristofer Vorwerk , Andrew Kennings , Doris T. Chen , Laleh Behjat, Floorplan repair using dynamic whitespace management, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Michael D. Moffitt , Jarrod A. Roy , Igor L. Markov , Martha E. Pollack, Constraint-driven floorplan repair, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.4, p.1-13, September 2008
	Kunihiko Yanagibashi , Yasuhiro Takashima , Yuichi Nakamura, A Relocation Method for Circuit Modifications, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E90-A n.12, p.2743-2751, December 2007