Efficient 3D modelling for extraction of interconnect capacitances in deep submicron dense layouts

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Efficient 3D modelling for extraction of interconnect capacitances in deep submicron dense layouts

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Article No. 115

Year of Publication: 1999

ISBN:1-58113-121-6

Authors

A. Toulouse	Université Montpellier II
D. Bernard	Université Montpellier II
C. Landrault	Université Montpellier II
P. Nouet	Université Montpellier II

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	1. P. Felix, "Interconnects for ULSI: State of the art and Future trends", Proc. ESSDERC, 1995, pp. 5-14.
	2	2. K. Rahmat and al., "A Scaling Scheme for Interconnect in Deep-Submicron Processes", Proc. IEDM, 1995, pp. 245-248.
	3	3. M.T. Bohr, "Interconnect Scaling - The Real Limiter to High Performance ULSI", Proc. IEDM'95, pp. 241-244.
	4	4. T. Sakurai, "Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI's", IEEE Trans. El. Dev., Vol. ED-40, No. 1, pp. 118-124, Jan. 1993.
	5	5. G. S. Samudra and al., "A set of Analytic Formulas for Capacitance of VLSI Interconnects of Trapezium Shape," IEEE Trans. El. Devices, vol. 41, no. 8, pp. 1467-1469, Aug. 1994.
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	8	8. C. Kortekaas, "Interconnect Capacitance Characterization for MOS-IC Process- and Circuit Design", Proc. IEEE ICMTS'88, pp. 39-44, Vol. 1, No. 1, Feb. 1988.
	9	9. Diva^TM Interactive Verification, Reference Manual, vol. 1, Cadence, Dec. 1992.
	10	10. S.Y. Oh and al, "3D GIPER Global Interconnect Parameter Extractor for Full-Chip Global Critical Analysis", Internationnal Electron Devices Meetings, pp. 615-618, 1996.
	11	11. B. Laquai and al., "A new method and test structure for easy determination of femto-Farad on-chip capacitances in a MOS process", Proc. ICMTS, Vol. 5, pp. 62-66, March 1992.
	12	12. D. Sylvester and al., "Investigation of Interconnect Capacitance Characterization Using Charge-Based Capacitance Measurement (CBCM) Technique and 3D Simulation", IEEE J. of Solid-State Circuits, Vol. 33, No. 3, March 1998.
	13	13. P. Nouet and al., "A New Test Structure for Interconnect Capacitance monitoring", ICMTS'97, pp. 81-84, March 1997.
	14	14. P. Nouet and al., "Use of Test Structures for Characterization and Modeling of Inter- and Intra-Layer Capacitances in a CMOS Process", IEEE Trans. on Semiconductor Manuf., Vol. 10, No. 2, pp. 233-241, May 1997.