Wavefront technology mapping

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Wavefront technology mapping

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Article No. 108

Year of Publication: 1999

ISBN:1-58113-121-6

Authors

Leon Stok	IBM TJ Watson Research Center, Yorktown Heights, NY
Mahesh A. Iyer	Synopsys Inc., Mountain View, CA
Andrew J. Sullivan	IBM Server Development, Fishkill, NY

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 8, Citation Count: 11

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Frederik Beeftink , Prabhakar Kudva , David Kung , Leon Stok, Gate-size selection for standard cell libraries, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.545-550, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.289084]
	2	[2] E. Detjens, R. Rudell, G. Gannot, A. Wang, and A. Sangiovanni-Vincentelli. Technology mapping in mis. In Proc of the Int. Conf on Computer Aided Design, pages 116-119, Nov 1987.
	3	Joel Grodstein , Eric Lehman , Heather Harkness , Bill Grundmann , Yosinatori Watanabe, A delay model for logic synthesis of continuously-sized networks, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.458-462, November 05-09, 1995, San Jose, California, United States
	4	Robert B. Hitchcock, Sr., Timing Verification and the Timing Analysis program, Proceedings of the 19th conference on Design automation, p.594-604, January 1982
	5	[5] R. HitchcockSr., G. Smith, and D. Cheng. Timing analysis of computer hardware. IBM J. Res. Develop., 26(1), January 1982.
	6	K. Keutzer, DAGON: technology binding and local optimization by DAG matching, Proceedings of the 24th ACM/IEEE conference on Design automation, p.341-347, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37940]
	7	[7] P. Kudva. Continuous optimizations in synthesis: The discretization problem. In Proc of Int. Workshop on Logic Synthesis , pages 408-419, June 1998.
	8	Yuji Kukimoto , Robert K. Brayton , Prashant Sawkar, Delay-optimal technology mapping by DAG covering, Proceedings of the 35th annual conference on Design automation, p.348-351, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277142]
	9	[9] E. Lehman, Y. Watanabe, J. Grodstein, and H. Harkness. Logic decomposition during technology mapping. IEEE Trans on CAD, 16(8):813-834, August 1997.
	10	Eric Lehman , Yosinori Watanabe , Joel Grodstein , Heather Harkness, Logic decomposition during technology mapping, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.264-271, November 05-09, 1995, San Jose, California, United States
	11	[11] R. Rudell. Logic synthesis for vlsi design. Technical report, University of California, Berkeley, 1989.
	12	K. L. Shepard , S. M. Carey , E. K. Cho , B. W. Curran , R. F. Hatch , D. E. Hoffman , S. A. McCabe , G. A. Northrop , R. Seigler, Design methodology for the S/390 parallel enterprise server G4 microprocessors, IBM Journal of Research and Development, v.41 n.4-5, p.515-547, July/Sept. 1997
	13	L. Stok , D. S. Kung , D. Brand , A. D. Drumm , L. N. Reddy , N. Hieter , D. J. Geiger , H. H. Chao , P. J. Osler , A. J. Sullivan, BooleDozer: logic synthesis for ASICs, IBM Journal of Research and Development, v.40 n.4, p.407-430, July 1996
	14	Ivan E. Sutherland , Robert F. Sproull, Logical effort: designing for speed on the back of an envelope, Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI, p.1-16, April 1991

CITED BY 11

	Leon Stok , Vivek Tiwari, Technology mapping, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Yiu-Hing Chan , Prabhakar Kudva , Lisa Lacey , Greg Northrop , Thomas Rosser, Physical synthesis methodology for high performance microprocessors, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Vinícius Correia , André Reis, Advanced technology mapping for standard-cell generators, Proceedings of the 17th symposium on Integrated circuits and system design, September 07-11, 2004, Pernambuco, Brazil
	Thomas Kutzschebauch , Leon Stok, Congestion aware layout driven logic synthesis, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Bo Hu , Yosinori Watanabe , Alex Kondratyev , Malgorzata Marek-Sadowska, Gain-based technology mapping for discrete-size cell libraries, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Chi-Shong Wang , Chingwei Yeh, Performance-driven technology mapping with MSG partition and selective gate duplication, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.4, p.953-973, October 2006
	F. S. Marques , L. S. Rosa, Jr. , R. P. Ribas , S. S. Sapatnekar , A. I. Reis, DAG based library-free technology mapping, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	S. K. Karandikar , S. S. Sapatnekar, Logical effort based technology mapping, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.419-422, November 07-11, 2004
	S. Chatterjee , A. Mishchenko , R. Brayton , X. Wang , T. Kam, Reducing structural bias in technology mapping, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.519-526, November 06-10, 2005, San Jose, CA
	Zile Wei , Donald Chai , A. Richard Newton , Andreas Kuehlmann, Fast Boolean Matching with Don't Cares, Proceedings of the 7th International Symposium on Quality Electronic Design, p.346-351, March 27-29, 2006
	Shrirang K. Karandikar , Sachin S. Sapatnekar, Fast Comparisons of Circuit Implementations, Proceedings of the conference on Design, automation and test in Europe, p.20910, February 16-20, 2004