Full scan fault coverage with partial scan

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Full scan fault coverage with partial scan

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Article No. 97

Year of Publication: 1999

ISBN:1-58113-121-6

Authors

Xijiang Lin	Mentor Graphics Corporation, Wilsonville, OR
Irith Pomeranz	Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA
Sudhakar M. Reddy	Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 6, Citation Count: 4

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	[1] E. Trischler, "Incomplete Scan Path with an Automatic Test Generation Methodology," Proc. of Intl. Test Conf., pp. 153-162, November 1980.
	2	Miron Abramovici , James J. Kulikowski , Rabindra K. Roy, The Best Flip-Flops to Scan, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.166-173, October 26-30, 1991
	3	Prashant S. Parikh , Miron Abramovici, Testability-based partial scan analysis, Journal of Electronic Testing: Theory and Applications, v.7 n.1-2, p.61-70, Aug./Oct. 1995 [doi>10.1007/BF00993314]
	4	Kee S. Kim , Charles R. Kime, Partial scan flip-flop selection by use of empirical testability, Journal of Electronic Testing: Theory and Applications, v.7 n.1-2, p.47-59, Aug./Oct. 1995 [doi>10.1007/BF00993313]
	5	[5] R. Gupta, R. Gupta, and M. A. Breuer, "BALLAST: A Methodology for Partial Scan Design," Fault Tolerant Computing Symposium, pp. 118-125, June 1989.
	6	A. Kunzmann , J. J. Wunderlich, An analytical approach to the partial scan problem, Journal of Electronic Testing: Theory and Applications, v.1 n.2, p.163-174, May 1990 [doi>10.1007/BF00137392]
	7	K.-T. Cheng , V. D. Agrawal, A Partial Scan Method for Sequential Circuits with Feedback, IEEE Transactions on Computers, v.39 n.4, p.544-548, April 1990 [doi>10.1109/12.54847]
	8	[8] D. H. Lee and S. M. Reddy, "On Determining Scan Flip-Flops in Partial Scan Design", Proc. of Intl. Conf. on Computer-Aided Design, pp. 322-325, Nov. 1990.
	9	[9] V. Chickermane and J.H. Patel, "An Optimization Based Approach to the Partial Scan Design Problem," Proc. of Intl. Test Conf., pp. 377-386, September 1990.
	10	Srimat T. Chakradhar , Arun Balakrishnan , Vishwani D. Agrawal, An exact algorithm for selecting partial scan flip-flops, Proceedings of the 31st annual conference on Design automation, p.81-86, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196285]
	11	Tatiana Orenstein , Zvi Kohavi , Irith Pomeranz, An optimal algorithm for cycle breaking in directed graphs, Journal of Electronic Testing: Theory and Applications, v.7 n.1-2, p.71-81, Aug./Oct. 1995 [doi>10.1007/BF00993315]
	12	Shang-E Tai , Debashis Bhattacharya, A three-stage partial scan design method to ease ATPG, Journal of Electronic Testing: Theory and Applications, v.7 n.1-2, p.95-104, Aug./Oct. 1995 [doi>10.1007/BF00993317]
	13	Dong Xiang , Srikanth Venkataraman , W. Kent Fuchs , Janak H. Patel, Partial scan design based on circuit state information, Proceedings of the 33rd annual conference on Design automation, p.807-812, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240670]
	14	Dong Xiang , Janak H. Patel, A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information, Proceedings of the IEEE International Test Conference on Test and Design Validity, p.548-557, October 20-25, 1996
	15	Arun Balakrishnan , Srimat T. Chakradhar, Peripheral Partitioning and Tree Decomposition for Partial Scan, Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing, p.181, January 04-07, 1998
	16	Vishiwani D. Agrawal , Kwang-Ting Cheng , Daniel D. Johnson , Tony Sheng Lin, Designing Circuits with Partial Scan, IEEE Design & Test, v.5 n.2, p.8-15, March 1988 [doi>10.1109/54.2032]
	17	[17] V. Chickermane and J.H. Patel, "A Fault Oriented Partial Scan Design Approach," Proc. of Intl. Conf. on CAD, pp. 400-403, November 1991.
	18	Insung Park , Dong Sam Ha , Gyoochan Sim, A New Method for Partial Scan Design Based on Propagation and Justification Requirements of Faults, Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test, p.413-422, October 21-25, 1995
	19	Vamsi Boppana , W. Kent Fuchs, Partial Scan Design Based on State Transition Modeling, Proceedings of the IEEE International Test Conference on Test and Design Validity, p.538-547, October 20-25, 1996
	20	Michael S. Hsiao , Gurjeet S. Saund , Elizabeth M. Rudnick , Janak H. Patel, Partial Scan Selection Based on Dynamic Reachability and Observability Information, Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing, p.174, January 04-07, 1998
	21	On Finding Undetectable and Redundant Faults in Synchronous Sequential Circuits, Proceedings of the International Conference on Computer Design, p.498, October 05-05, 1998
	22	Xijiang Lin , Irith Pomeranz , Sudhakar M. Reddy, MIX: A Test Generation System for Synchronous Sequential Circuits, Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing, p.456, January 04-07, 1998
	23	I. Pomeranz , S. M. Reddy, Classification of Faults in Synchronous Sequential Circuits, IEEE Transactions on Computers, v.42 n.9, p.1066-1077, September 1993 [doi>10.1109/12.241596]

CITED BY 4

	Dong Xiang , Janak H. Patel, Partial Scan Design Based on Circuit State Information and Functional Analysis, IEEE Transactions on Computers, v.53 n.3, p.276-287, March 2004
	Irith Pomeranz , Sudhakar M. Reddy, On undetectable faults in partial scan circuits, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.82-86, November 10-14, 2002, San Jose, California
	Margrit R. Krug , Marcelo S. Moraes , Marcelo S. Lubaszewski, Using a software testing technique to identify registers for partial scan implementation, Proceedings of the 19th annual symposium on Integrated circuits and systems design, August 28-September 01, 2006, Ouro Preto, MG, Brazil
	Loganathan Lingappan , Niraj K. Jha, Satisfiability-based automatic test program generation and design for testability for microprocessors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.5, p.518-530, May 2007