Functional verification methodology for microprocessors using the Genesys test-program generator

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Functional verification methodology for microprocessors using the Genesys test-program generator

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Article No. 92

Year of Publication: 1999

ISBN:1-58113-121-6

Authors

Laurent Fournier	IBM Haiga Research Lab
Yaron Arbetman	IBM Haiga Research Lab
Moshe Levinger	IBM Haiga Research Lab

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 26, Citation Count: 16

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	[1] Y. Lichtenstein, Y. Malka and A. Aharon, "Model-Based Test Generation For Processor Design Verification", Innovative Applications of Artificial Intelligence (IAAI), AAAI Press, 1994.
	2	[2] H.P. Sharangpani, M.L. Barton, "Statistical Analysis of Floating Point Flaw in the Pentium Processor", Intel Corporation, 1994.
	3	Françoise Casaubieilh , Anthony McIsaac , Mike Benjamin , Mike Bartley , François Pogodalla , Frédéric Rocheteau , Mohamed Belhadj , Jeremy Eggleton , Gérard Mas , Geoff Barrett , Christian Berthet, Functional verification methodology of Chameleon processor, Proceedings of the 33rd annual conference on Design automation, p.421-426, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240599]
	4	Aharon Aharon , Dave Goodman , Moshe Levinger , Yossi Lichtenstein , Yossi Malka , Charlotte Metzger , Moshe Molcho , Gil Shurek, Test program generation for functional verification of PowerPC processors in IBM, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.279-285, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217542]
	5	Alberto L. Sangiovanni-Vincentelli , Patrick C. McGeer , Alexander Saldanha, Verification of electronic systems, Proceedings of the 33rd annual conference on Design automation, p.106-111, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240539]
	6	James Monaco , David Holloway , Rajesh Raina, Functional verification methodology for the PowerPC 604 microprocessor, Proceedings of the 33rd annual conference on Design automation, p.319-324, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240579]
	7	Michael Katrowitz , Lisa M. Noack, I'm done simulating; now what? Verification coverage analysis and correctness checking of the DEC chip 21164 Alpha microprocessor, Proceedings of the 33rd annual conference on Design automation, p.325-330, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240580]
	8	[8] D. Lewin, L. Fournier, M. Levinger, E. Roytman, G. Shurek, "Constraint Satisfaction for Test Program Generation", IEEE 14th Phoenix Conference on Computers and Communications, 1995.
	9	[9] Intel Pentium II flag erratum, Intel home page at: http:// developer.intel.com/design/news/flag/tech.htm
	10	Gopi Ganapathy , Ram Narayan , Glenn Jorden , Denzil Fernandez , Ming Wang , Jim Nishimura, Hardware emulation for functional verification of K5, Proceedings of the 33rd annual conference on Design automation, p.315-318, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240578]

CITED BY 18

	Bob Bentley, Validating the intel pentium 4 microprocessor, Proceedings of the 38th conference on Design automation, p.244-248, June 2001, Las Vegas, Nevada, United States
	Lieh-Ming Wu , Kuochen Wang , Chuang-Yi Chiu, A BNF-based automatic test program generator for compatible microprocessor verification, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.1, p.105-132, January 2004
	Abraham Ziv , Laurent Fournier, Solving the generalized mask constraint for test generation of binary floating point add operation, Theoretical Computer Science, v.291 n.2, p.183-201, 5 January 2003
	Shai Fine , Avi Ziv, Coverage directed test generation for functional verification using bayesian networks, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Laurent Fournier , Anatoly Koyfman , Moshe Levinger, Developing an architecture validation suite: application to the PowerPC architecture, Proceedings of the 36th ACM/IEEE conference on Design automation, p.189-194, June 21-25, 1999, New Orleans, Louisiana, United States
	Rina Dechter , Kalev Kask , Eyal Bin , Roy Emek, Generating random solutions for constraint satisfaction problems, Eighteenth national conference on Artificial intelligence, p.15-21, July 28-August 01, 2002, Edmonton, Alberta, Canada
	Sigal Asaf , Eitan Marcus , Avi Ziv, Defining coverage views to improve functional coverage analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Karina R. G. da Silva , Elmar U. K. Melcher , Guido Araujo , Valdiney Alves Pimenta, An automatic testbench generation tool for a SystemC functional verification methodology, Proceedings of the 17th symposium on Integrated circuits and system design, September 07-11, 2004, Pernambuco, Brazil
	Allon Adir , Eli Almog , Laurent Fournier , Eitan Marcus , Michal Rimon , Michael Vinov , Avi Ziv, Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification, IEEE Design & Test, v.21 n.2, p.84-93, March 2004
	Oded Lachish , Eitan Marcus , Shmuel Ur , Avi Ziv, Hole analysis for functional coverage data, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Allon Adir , Hezi Azatchi , Eyal Bin , Ofer Peled , Kirill Shoikhet, A generic micro-architectural test plan approach for microprocessor verification, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	A. Y. Duale , M. H. Decker , H.-G. Zipperer , M. Aharoni , T. J. Bohizic, Decimal floating-point in z9: an implementation and testing perspective, IBM Journal of Research and Development, v.51 n.1/2, p.217-227, January 2007
	Shireesh Verma , Ian G. Harris , Kiran Ramineni, Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Young-Su Kwon , Chong-Min Kyung, Functional Coverage Metric Generation from Temporal Event Relation Graph, Proceedings of the conference on Design, automation and test in Europe, p.10670, February 16-20, 2004
	Hezi Azatchi , Laurent Fournier , Eitan Marcus , Shmuel Ur , Avi Ziv , Keren Zohar, Advanced Analysis Techniques for Cross-Product Coverage, IEEE Transactions on Computers, v.55 n.11, p.1367-1379, November 2006
	Shai Fine , Ari Freund , Itai Jaeger , Yishay Mansour , Yehuda Naveh , Avi Ziv, Harnessing Machine Learning to Improve the Success Rate of Stimuli Generation, IEEE Transactions on Computers, v.55 n.11, p.1344-1355, November 2006
	E. Bin , R. Emek , G. Shurek , A. Ziv, Using a constraint satisfaction formulation and solution techniques for random test program generation, IBM Systems Journal, v.41 n.3, p.386-402, July 2002
	C. A. Reed , D. J. Thygesen, Pseudorandom verification and emulation of an MPEG-2 transport demultiplexor, IBM Journal of Research and Development, v.43 n.4, p.533-544, July 1999