| Efficient techniques for accurate extraction and modeling of substrate coupling in mixed-signal IC's |
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Design, Automation, and Test in Europe
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Proceedings of the conference on Design, automation and test in Europe
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Munich, Germany
Article No. 84
Year of Publication: 1999
ISBN:1-58113-121-6
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Authors
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João Paulo Costa
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INESC/Cadence European Laboratories, Department of Electrical and Computer Engineering, Instituto Superior Técnico, Lisboa, Portugal
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Mike Chou
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Research Laboratory of Electronics, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA
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L. Miguel Silveira
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Cadence European Laboratories, Department of Electrical and Computer Engineering, Instituto Superior Técnico, Lisboa, Portugal
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| Bibliometrics |
Downloads (6 Weeks): 2, Downloads (12 Months): 17, Citation Count: 2
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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[1] David K. Su, Marc J. Loinaz, Shoichi Masui, and Bruce A. Wooley. Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits. IEEE Journal of Solid-State Circuits , 28(4):420-430, April 1993.
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[2] T. A. Johnson, R. W. Knepper, V. Marcellu, and W. Wang. Chip substrate resistance modeling technique for integrated circuit design. IEEE Transactions on Computer-Aided Design of Integrated Circuits , CAD-3(2):126-134, 1984.
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[3] Ranjit Gharpurey. Modeling and Analysis of Substrate Coupling in Integrated Circuits. PhD thesis, Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA, June 1995.
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[4] Bram Nauta and Gian Hoogzaad. How to deal with substrate noise in analog CMOS circuits. In European Conference on Circuit Theory and Design, pages Late 12:1-6, Budapest, Hungary, September 1997.
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[5] Nishath Verghese. Extraction and Simulation Techniques for Substrate-Coupled Noise in Mixed-Signal Integrated Circuits. PhD thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, August 1995.
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[6] Sujoy Mitra, R. A. Rutenbar, L. R. Carley, and D. J. Allstot. A methodology for rapid estimation of substrate-coupled switching noise. In IEEE 1995 Custom Integrated Circuits Conference, pages 129- 132, 1995.
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[7] Balsha Stanisic, Nishath K. Verghese, Rob A. Rutenbar, L. Richard Carley, and David J. Allstot. Addressing substrate coupling in mixed-mode IC's: Simulation and power distribution systems. IEEE Journal of Solid-State Circuits, 29(3):226-237, March 1994.
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T. Smedes , N. P. van der Meijs , A. J. van Genderen, Extraction of circuit models for substrate cross-talk, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.199-206, November 05-09, 1995, San Jose, California, United States
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[10] R. Gharpurey and R. G. Meyer. Modeling and analysis of substrate coupling in integrated circuits. In IEEE 1995 Custom Integrated Circuits Conference, pages 125-128, 1995.
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[11] Nishath K. Verghese, David J. Allstot, and Mark A. Wolfe. Verification techniques for substrate coupling and their application to mixed-signal IC design. IEEE Journal of Solid-State Circuits, 31(3):354-365, March 1996.
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J.-P. Costa , M. Chou , L. M. Silveira, Efficient techniques for accurate modeling and simulation of substrate coupling in mixed-signal IC's, Proceedings of the conference on Design, automation and test in Europe, p.892-898, February 23-26, 1998, Le Palais des Congrés de Paris, France
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[14] K. Nabors and J. White. Fast capacitance extraction of general three-dimensional structures. IEEE Transactions on Microwave Theory and Techniques, June 1992.
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[15] W. H. Press, S. A. Teukolsky, W. T. Vetterling, and B. P. Flannery. Numerical Recipies in C. Cambridge University Press, second edition, 1992.
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[17] V. Rohklin. Rapid solution of integral equation of classical potential theory. J. Comput. Phys., 60:187-207, 1985.
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[20] Ranjit Gharpurey and Robert G. Meyer. Modeling and analysis of substrate coupling in integrated circuits. IEEE Journal of Solid-State Circuits, 31(3):344-353, March 1996.
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