Automating the sizing of analog CMOS circuits by consideration of structural constraints

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Automating the sizing of analog CMOS circuits by consideration of structural constraints

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Article No. 69

Year of Publication: 1999

ISBN:1-58113-121-6

Authors

R. Schwencker	Technical University of Munich, Germany, and Siemens, Semiconductor Group, Munich, Germany
J. Eckmueller	Semiconductor Group, Munich, Germany
H. Graeb	Technical University of Munich, Germany
K. Antreich	Technical University of Munich, Germany

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 7, Citation Count: 3

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	[1] K. J. Antreich, P. Leibner, and F. Pörnbacher. Nominal design of integrated circuits on circuit level by interactive optimization. IEEE Trans. Circuits and Systems (CAS), 35:1501-1511, 1988.
	2	J. Ecküller , M. Gröpl , H. Gräb, Hierarchical characterization of analog integrated CMOS circuits, Proceedings of the conference on Design, automation and test in Europe, p.636-643, February 23-26, 1998, Le Palais des Congrés de Paris, France
	3	[3] G. Gielen, H. Walscharts, and W. Sansen. Analog circuit design optimization based on symbolic simulation and simulated annealing. IEEE Journal on Solid-State Circuits, 25:707-713, 1990.
	4	[4] P. E. Gill, W. Murray, and M. H. Wright. Practical Optimization . Academic Press. Inc., London, 1981.
	5	[5] A. E. E. S. GmbH. OPSIM User's Manual. Ulm, 1993.
	6	[6] D. W. Marquardt. An algorithm for least-squares estimation of nonlinear parameters. J. Soc. Ind. App. Math., 11:431-441, 1963.
	7	[7] W. Nye, D. Riley, A. Sangiovanni-Vincentelli, and A. Tits. Delight.spice: An optimization-based system for the design of integrated circuits. IEEE Trans. on Computer-Aided Design (CAD), 7:501-519, 1988.
	8	[8] F. Pörnbacher. A new method supporting the nominal design of analog integrated circuits with regard to constraints. In ECCTD, pages 614-618, 1989.

CITED BY 3

	R. Schwencker , F. Schenkel , H. Graeb , K. Antreich, The generalized boundary curve — a common method for automatic nominal design centering of analog circuits, Proceedings of the conference on Design, automation and test in Europe, p.42-47, March 27-30, 2000, Paris, France
	Hongzhou Liu , Amit Singhee , Rob A. Rutenbar , L. Richard Carley, Remembrance of circuits past: macromodeling by data mining in large analog design spaces, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	H. Graeb , S. Zizala , J. Eckmueller , K. Antreich, The sizing rules method for analog integrated circuit design, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California