A DAG-based design approach for reconfigurable VLIW processors

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A DAG-based design approach for reconfigurable VLIW processors

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Article No. 57

Year of Publication: 1999

ISBN:1-58113-121-6

Authors

Cesare Alippi	Politecnico di Milano, Italy
William Fornaciari	Politecnico di Milano, Italy
Laura Pozzi	Politecnico di Milano, Italy
Mariagiovanna Sami	Politecnico di Milano, Italy

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 33, Citation Count: 11

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Rahul Razdan , Michael D. Smith, A high-performance microarchitecture with hardware-programmable functional units, Proceedings of the 27th annual international symposium on Microarchitecture, p.172-180, November 30-December 02, 1994, San Jose, California, United States [doi>10.1145/192724.192749]
	2	S. Hauck , T. W. Fry , M. M. Hosler , J. P. Kao, The Chimaera reconfigurable functional unit, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.87, April 16-18, 1997
	3	[3] C. Alippi, W. Fornaciari, L. Pozzi, and M.G. Sami. A DAG-Based Design Approach for Reconfigurable VLIW Processors. Technical Report 98-104, Politecnico di Milano.
	4	Mary W. Hall , Jennifer M. Anderson , Saman P. Amarasinghe , Brian R. Murphy , Shih-Wei Liao , Edouard Bugnion , Monica S. Lam, Maximizing Multiprocessor Performance with the SUIF Compiler, Computer, v.29 n.12, p.84-89, December 1996 [doi>10.1109/2.546613]

CITED BY 11

	Bhuvan Middha , Anup Gangwar , Anshul Kumar , M. Balakrishnan , Paolo Ienne, A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional units, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
	Kubilay Atasu , Laura Pozzi , Paolo Ienne, Automatic application-specific instruction-set extensions under microarchitectural constraints, International Journal of Parallel Programming, v.31 n.6, p.411-428, December 2003
	Kubilay Atasu , Laura Pozzi , Paolo Ienne, Automatic application-specific instruction-set extensions under microarchitectural constraints, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Partha Biswas , Vinay Choudhary , Kubilay Atasu , Laura Pozzi , Paolo Ienne , Nikil Dutt, Introduction of local memory elements in instruction set extensions, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Kubilay Atasu , Günhan Dündar , Can Özturan, An integer linear programming approach for identifying instruction-set extensions, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
	Carlo Galuzzi , Elena Moscu Panainte , Yana Yankova , Koen Bertels , Stamatis Vassiliadis, Automatic selection of application-specific instruction-set extensions, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
	Monica Magalhães Pereira , Sílvio R. F. de Araújo , Bruno C. de Gliveira , Ivan Saraiva Silva, Using traditional loop unrolling to fit application on a new hybrid reconfigurable architecture, Proceedings of the 2008 ACM symposium on Applied computing, March 16-20, 2008, Fortaleza, Ceara, Brazil
	Fei Sun , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha, A Scalable Application-Specific Processor Synthesis Methodology, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.283, November 09-13, 2003
	Francisco Barat , Murali Jayapala , Pieter Op de Beeck , Geert Deconinck , K. U. Leuven, Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.338, January 07-11, 2002
	Monica Magalhaes Pereira , Bruno Cruz de Oliveira , Ivan Saraiva Silva, RoSA: a reconfigurable stream-based architecture, Proceedings of the 20th annual conference on Integrated circuits and systems design, September 03-06, 2007, Copacabana, Rio de Janeiro
	Partha Biswas , Sudarshan Banerjee , Nikil Dutt , Laura Pozzi , Paolo Ienne, ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement, Proceedings of the conference on Design, Automation and Test in Europe, p.1246-1251, March 07-11, 2005