MOCSYN

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MOCSYN: multiobjective core-based single-chip system synthesis

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Article No. 55

Year of Publication: 1999

ISBN:1-58113-121-6

Authors

Robert P. Dick	Department of Electrical Engineering, Princeton University, Princeton, NJ
Niraj K. Jha	Department of Electrical Engineering, Princeton University, Princeton, NJ

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 15, Citation Count: 19

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 19

	Jiong Luo , Niraj K. Jha, Battery-aware static scheduling for distributed real-time embedded systems, Proceedings of the 38th conference on Design automation, p.444-449, June 2001, Las Vegas, Nevada, United States
	Nacer-Eddine Zergainoh , Katalin Popovici , Ahmed Jerraya , Pascal Urard, IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Niraj K. Jha, Low power system scheduling and synthesis, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Byoung-Woon Kim , Chong-Min Kyung, Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.240-252, June 2002
	Jiong Luo , Niraj K. Jha, Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Bita Gorjiara , Nader Bagherzadeh , Pai Chou, An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Bita Gorji-Ara , Pai Chou , Nader Bagherzadeh , Mehrdad Reshadi , David Jensen, Fast and efficient voltage scheduling by evolutionary slack distribution, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.659-662, January 27-30, 2004, Yokohama, Japan
	Jian Liang , Andrew Laffely , Sriram Srinivasan , Russell Tessier, An architecture and compiler for scalable on-chip communication, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.711-726, July 2004
	Matthias Gries, Methods for evaluating and covering the design space during early design development, Integration, the VLSI Journal, v.38 n.2, p.131-183, December 2004
	Sudeep Pasricha , Nikil Dutt , Elaheh Bozorgzadeh , Mohamed Ben-Romdhane, Floorplan-aware automated synthesis of bus-based communication architectures, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Zhe Ma , Francky Catthoor, Scalable performance-energy trade-off exploration of embedded real-time systems on multiprocessor platforms, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Sudeep Pasricha , Nikil D. Dutt , Elaheh Bozorgzadeh , Mohamed Ben-Romdhane, FABSYN: floorplan-aware bus architecture synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.3, p.241-253, March 2006
	Jiong Luo , Niraj K. Jha , Li-Shiuan Peh, Simultaneous dynamic voltage scaling of processors and communication links in real-time distributed embedded systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.4, p.427-437, April 2007
	Pallav Gupta , Lin Zhong , Niraj K. Jha, A High-level Interconnect Power Model for Design Space Exploration, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.551, November 09-13, 2003
	Jiong Luo , Niraj K. Jha, Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.719, January 07-11, 2002
	Yunsi Fei , Niraj K. Jha, Functional Partitioning for Low Power Distributed Systems of Systems-on-a-chip, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.274, January 07-11, 2002
	Nattawut Thepayasuwan , Alex Doboli, Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip, Proceedings of the conference on Design, automation and test in Europe, p.10108, February 16-20, 2004
	Nikolaos D. Liveris , Prithviraj Banerjee, Power Aware Interface Synthesis for Bus-Based SoC Designs, Proceedings of the conference on Design, automation and test in Europe, p.20864, February 16-20, 2004
	Bita Gorjiara , Nader Bagherzadeh , Pai H. Chou, Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.4, p.39-es, September 2007