Kernel scheduling in reconfigurable computing

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Kernel scheduling in reconfigurable computing

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Article No. 21

Year of Publication: 1999

ISBN:1-58113-121-6

Authors

R. Maestre	Departamento de Arquitectura de Computadores y Automática, Universidad Complutense, Madrid, Spain
F. J. Kurdahi	Department of Electrical and Computer Engineering, University of California, Irvine, CA
N. Bagherzadeh	Department of Electrical and Computer Engineering, University of California, Irvine, CA
H. Singh	Department of Electrical and Computer Engineering, University of California, Irvine, CA
R. Hermida	Departamento de Arquitectura de Computadores y Automática, Universidad Complutense, Madrid, Spain
M. Fernandez	Departamento de Arquitectura de Computadores y Automática, Universidad Complutense, Madrid, Spain

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 9, Citation Count: 19

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	[1] I. Ouaiss, S. Govindarajan, V. Srinivasan, M. Kaul and R. Vemuri, "An Integrated Partitioning and Synthesis system for Dynamically Reconfigurable Multi-FPGA Architectures", 5th Reconfigurable Architectures Workshop, 1998 (RAW'98).
	2	Milan Vasilko , Djamel Ait-Boudaoud, Architectural Synthesis Techniques for Dynamically Reconfigurable Logic, Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, p.290-296, September 23-25, 1996
	3	[3] M. Vasilko and D. Ait-Boudaoud, "Scheduling for Dynamically Reconfigurable FPGAs", in Proceeding of International Workshop on Logic and Architecture Synthesis, IFIP TC10 WG10.5, Grenoble, France, Dec. 18- 19, 1995, pp. 328-336.
	4	Karthikeya M. Gajjala Purna , Dinesh Bhatia, Temporal Partitioning and Scheduling for Reconfigurable Computing, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.329, April 15-17, 1998
	5	M. Kaul , R. Vemuri, Optimal temporal partitioning and synthesis for reconfigurable architectures, Proceedings of the conference on Design, automation and test in Europe, p.389-397, February 23-26, 1998, Le Palais des Congrés de Paris, France
	6	[6] H. Singh, M. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, T. Lang, R. Heaton and E. M. C. Filho, "MorphoSys: An Integrated Re-configurable Architecture", Proceedings of the NATO Symposium on System Concepts and Integration, Monterey, CA, April 1998.
	7	Elliot Waingold , Michael Taylor , Devabhaktuni Srikrishna , Vivek Sarkar , Walter Lee , Victor Lee , Jang Kim , Matthew Frank , Peter Finch , Rajeev Barua , Jonathan Babb , Saman Amarasinghe , Anant Agarwal, Baring It All to Software: Raw Machines, Computer, v.30 n.9, p.86-93, September 1997 [doi>10.1109/2.612254]
	8	[8] E. Tau, D. Chen, I. Eslick, J. Brown and A. Dehon, "A First Generation DPGA Implementation", Third Canadian Workshop of Field-Programmable Devices, May 29 - Jun 1, 1995.
	9	[9] E. Mirsky and A. Dehon, "MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources", Proc, of IEEE Symposium on FPGAs for Custom Computing Machines, IEEE CS Press, p. 157-166, 1996.
	10	J. R. Hauser , J. Wawrzynek, Garp: a MIPS processor with a reconfigurable coprocessor, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.12, April 16-18, 1997
	11	Arthur Abnous , Christopher Christensen , Jeffrey Gray , John Lenell , Andrew Naylor , Nader Bagherzadeh, Design and implementation of the “Tiny RISC” microprocessor, Microprocessors & Microsystems, v.16 n.4, p.187-193, May 1992 [doi>10.1016/0141-9331(92)90021-K]

CITED BY 19

	Juanjo Noguera , Rosa M. Badia, HW/SW codesign techniques for dynamically reconfigurable architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.4, p.399-415, August 2002
	Bo-Sung Kim , Jun-Dong Cho, Maximizing memory data reuse for lower power motion estimation, Proceedings of the 10th Great Lakes symposium on VLSI, p.133-138, March 02-04, 2000, Chicago, Illinois, United States
	Rafael Maestre , Milagros Fernandez , Fadi J. Kurdahi , Nader Bagherzadeh , Hartej Singh, Configuration management in multi-context reconfigurable systems for simultaneous performance and power optimizations, Proceedings of the 13th international symposium on System synthesis, September 20-22, 2000, Madrid, Spain
	Rafael Maestre , Fadi J. Kurdahi , Milagros Fernández , Roman Hermida , Nader Bagherzadeh , Hartej Singh, A framework for reconfigurable computing: task scheduling and context management, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.858-873, 12/1/2001
	Hartej Singh , Guangming Lu , Eliseu Filho , Rafael Maestre , Ming-Hau Lee , Fadi Kurdahi , Nader Bagherzadeh, MorphoSys: case study of a reconfigurable computing system targeting multimedia applications, Proceedings of the 37th conference on Design automation, p.573-578, June 05-09, 2000, Los Angeles, California, United States
	Girish Venkataramani , Walid Najjar , Fadi Kurdahi , Nader Bagherzadeh , Wim Bohm, A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture, Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems, November 16-17, 2001, Atlanta, Georgia, USA
	Marcos Sanchez-Elez , Milagros Fernández , Roman Hermida , Rafael Maestre , Fadi Kurdahi , Nader Bagherzadeh, A data scheduler for multi-context reconfigurable architectures, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Juanjo Noguera , Rosa M. Badia, System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures, Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, October 30-November 01, 2003, San Jose, California, USA
	Juanjo Noguera , Rosa M. Badia, Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
	Hassan Diab , Issam Damaj, Cyclic coding algorithms under MorphoSys reconfigurable computing system, Advances in Engineering Software, v.34 n.2, p.61-72, 14 February 2003
	Sunghyun Lee , Sungjoo Yoo , Kiyoung Choi, Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
	Arezou Koohi , Nader Bagherzadeh , Chengzi Pan, A fast parallel reed-solomon decoder on a reconfigurable architecture, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, October 01-03, 2003, Newport Beach, CA, USA
	Girish Venkataramani , Walid Najjar , Fadi Kurdahi , Nader Bagherzadeh , Wim Bohm , Jeff Hammes, Automatic compilation to a coarse-grained reconfigurable system-opn-chip, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.4, p.560-589, November 2003
	Juanjo Noguera , Rosa M. Badia, Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling, ACM Transactions on Embedded Computing Systems (TECS), v.3 n.2, p.385-406, May 2004
	Elena Moscu Panainte , Koen Bertels , Stamatis Vassiliadis, Compiler-driven FPGA-area allocation for reconfigurable computing, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Philip Garcia , Katherine Compton , Michael Schulte , Emily Blem , Wenyin Fu, An overview of reconfigurable hardware in embedded systems, EURASIP Journal on Embedded Systems, v.2006 n.1, p.13-13, January 2006
	M. Sanchez-Elez , M. Fernandez , M. Anido , H. Du , N. Bagherzadeh , R. Hermida, Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures, Proceedings of the conference on Design, Automation and Test in Europe, p.10036, March 03-07, 2003
	R. Maestre , M. Fernandez , R. Hermida , N. Bagherzadeh, A Framework for Scheduling and Context Allocation in Reconfigurable Computing, Proceedings of the 12th international symposium on System synthesis, p.134, November 01-04, 1999
	Benoit Miramond , Jean-Marc Delosme, Design Space Exploration for Dynamically Reconfigurable Architectures, Proceedings of the conference on Design, Automation and Test in Europe, p.366-371, March 07-11, 2005