Automatic verification of scheduling results in high-level synthesis

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Automatic verification of scheduling results in high-level synthesis

Full text

Pdf (67 KB)

Source

Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Article No. 12

Year of Publication: 1999

ISBN:1-58113-121-6

Authors

Hans Eveking	Department of Electrical and Computer Engineering, Darmstadt University of Technology, Darmstadt, Germany
Holger Hinrichsen	Department of Electrical and Computer Engineering, Darmstadt University of Technology, Darmstadt, Germany
Gerd Ritter	Department of Electrical and Computer Engineering, Darmstadt University of Technology, Darmstadt, Germany

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 5, Citation Count: 5

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/307418.307449 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Pranav Ashar , Subhrajit Bhattacharya , Anand Raghunathan , Akira Mukaiyama, Verification of RTL generated from scheduled behavior in a high-level synthesis flow, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.517-524, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.289080]
	2	[2] A.J. Bernstein. Analysis of programs for parallel processing. IEEE Trans. Computers, pages 757-763, 1966.
	3	[3] C. Blumenröhr, D. Eisenbiegler, and R. Kumar. Applicability of formal synthesis illustrated via scheduling. In Proc. IWLAS'96, 1996.
	4	Jerry R. Burch , David L. Dill, Automatic verification of Pipelined Microprocessor Control, Proceedings of the 6th International Conference on Computer Aided Verification, p.68-80, June 21-23, 1994
	5	[5] R. Camposano. Path-based scheduling for synthesis. IEEE Trans. on CAD, 10(1):8593, 1991.
	6	David Cyrluk, Inverting the Abstraction Mapping: A Methodology for Hardware Verification, Proceedings of the First International Conference on Formal Methods in Computer-Aided Design, p.172-186, November 06-08, 1996
	7	[7] H. Eveking, H. Hinrichsen, and G. Ritter. Formally correct construction of pipelined processors. Technical Report 98- 6-1, Darmstadt University of Technology, Dept. of Electrical and Computer Engineering, 1998.
	8	Fridtjof Feldbusch , Ramayya Kumar, Verification of synthesized circuits at register transfer level with flow graphs, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	9	[9] V.M. Glushkov. Automata theory and formal microprogram transformations. Kibernetika, 1(5):19, 1965.
	10	[10] H. Hinrichsen, H. Eveking, and G. Ritter. Formal synthesis for pipeline design. In Proc. DMTCS+CATS'98. Springer DMTCS, 1998.
	11	Andreas Kuehlmann , Florian Krohm, Equivalence checking using cuts and heaps, Proceedings of the 34th annual conference on Design automation, p.263-268, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266090]
	12	Ramayya Kumar , Christian Blumenröhr , Dirk Eisenbiegler , Detlef Schmid, Formal Synthesis in Circuit Design - A Classification and Survey, Proceedings of the First International Conference on Formal Methods in Computer-Aided Design, p.294-309, November 06-08, 1996
	13	Matthias Mutz, Automatic post-synthesis verification support for a high level synthesis step by using the HOL theorem proving system, Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification, p.291-308, October 16-18, 1997
	14	Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis, Proceedings of the International Conference on Computer Design, p.392, October 05-05, 1998
	15	[15] N. Park and A.C. Parker. Sehwa: a software package for synthesis of pipelines from behavioral specifications. IEEE Transactions on CAD, 7(3):356-370, 1988.
	16	Maher Rahmouni , Ahmed A. Jerraya, Formulation and evaluation of scheduling techniques for control flow graphs, Proceedings of the conference on European design automation, p.386-391, September 18-22, 1995, Brighton, England
	17	C. A. J. van Eijk, Sequential equivalence checking without state space traversal, Proceedings of the conference on Design, automation and test in Europe, p.618-623, February 23-26, 1998, Le Palais des Congrés de Paris, France

CITED BY 5

	E. Teica , R. Radhakrishnan , R. Vemuri, On the verification of synthesized designs using automatically generated transformational witnesses, Proceedings of the conference on Design, automation and test in Europe, p.798, March 2001, Munich, Germany
	Kai Kapp , Viktor Sabelfeld, Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Chandan Karfa , Dipankar Sarkar , Chittaranjan Mandal , Chris Reade, Hand-in-hand verification of high-level synthesis, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	C Karfa , C Mandal , D Sarkar , S R. Pentakota , Chris Reade, A Formal Verification Method of Scheduling in High-level Synthesis, Proceedings of the 7th International Symposium on Quality Electronic Design, p.71-78, March 27-29, 2006
	Youngsik Kim , Nazanin Mansouri, Automated formal verification of scheduling with speculative code motions, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA