A new parameterizable power macro-model for datapath components

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A new parameterizable power macro-model for datapath components

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Article No. 8

Year of Publication: 1999

ISBN:1-58113-121-6

Authors

Gerd Jochens	OFFIS Research Institute, Oldenburg
Lars Kruse	OFFIS Research Institute, Oldenburg
Eike Schmidt	OFFIS Research Institute, Oldenburg
Wolfgang Nebel	OFFIS Research Institute, Oldenburg

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 12, Citation Count: 11

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	[1] Macii, E.; Pedram, M.; Somenzi, F.: High level power modeling, estimation and optimization. To appear in Trans. on Design Automation of Electronic Systems, 1998.
	2	Paul E. Landman , Jan M. Rabaey, Architectural power analysis: the dual bit type method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.2, p.173-187, June 1995 [doi>10.1109/92.386219]
	3	[3] Landman, P. E.; Rabaey, J. M.: Activity-Sensitive Architectural Power Analysis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 6, pp. 571-587, 1996.
	4	A. Bogliolo , L. Benini , G. De Micheli, Adaptive least mean square behavioral power modeling, Proceedings of the 1997 European conference on Design and Test, p.404, March 17-20, 1997
	5	E. Musoll , J. Cortadella, Scheduling and resource binding for low power, Proceedings of the 8th international symposium on System synthesis, p.104-109, September 13-15, 1995, Cannes, France [doi>10.1145/224486.224523]
	6	E. Musoll , J. Cortadella, High-level synthesis techniques for reducing the activity of functional units, Proceedings of the 1995 international symposium on Low power design, p.99-104, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224099]
	7	Jui-Ming Chang , Massoud Pedram, Register allocation and binding for low power, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.29-35, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217502]
	8	M. Pedram , J. Chang, Module assignment for low power, Proceedings of the conference on European design automation, p.376-381, September 1996, Geneva, Switzerland
	9	[9] Landman, P. E.; Rabaey, J. M.: Power Estimation for High Level Synthesis. IEEE European Design Automation Conference, 1993.
	10	[10] Ramprasad, R.; Shanbhag, N. R.; Hajj, N.: Analytical Estimation of Signal Transition Activity from Word-Level Statistics. IEEE Trans. on Computer-Aided Design of Integr. Circuits and Systems, Vol. 16, No. 7, pp. 718-733, 1997.
	11	Chi-Ying Tsui , Kai-Keung Chan , Qing Wu , Chih-Shun Ding , Massoud Pedram, A power estimation framework for designing low power portable video applications, Proceedings of the 34th annual conference on Design automation, p.421-424, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266186]

CITED BY 11

	Eike Schmidt , Gerd von Cölln , Lars Kruse , Frans Theeuwen , Wolfgang Nebel, Memory power models for multilevel power estimation and optimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.2, p.106-108, April 2002
	Ansgar Stammermann , Lars Kruse , Wolfgang Nebel , Alexander Pratsch , Eike Schmidt , Milan Schulte , Arne Schulz, System level optimization and design space exploration for low power, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Alessandro Bogliolo , Roberto Corgnati , Enrico Macii , Massimo Poncino, Parameterized RTL power models for combinational soft macros, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.284-288, November 07-11, 1999, San Jose, California, United States
	Michael Eiermann , Walter Stechele, Novel modeling techniques for RTL power estimation, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Lars Kruse , Eike Schmidt , Gerd Jochens , Ansgar Stammermann , Wolfgang Nebel, Lower bound estimation for low power high-level synthesis, Proceedings of the 13th international symposium on System synthesis, September 20-22, 2000, Madrid, Spain
	Lars Kruse , Eike Schmidt , Gerd Jochens , Wolfgang Nebel, Lower and upper bounds on the switching activity in scheduled data flow graphs, Proceedings of the 1999 international symposium on Low power electronics and design, p.115-120, August 16-17, 1999, San Diego, California, United States
	Nam Sung Kim , Todd Austin , Trevor Mudge , Dirk Grunwald, Challenges for architectural level power modeling, Power aware computing, Kluwer Academic Publishers, Norwell, MA, 2002
	Alessandro Bolgiolo , Roberto Corgnati , Enrico Macii , Massimo Poncino, Parameterized RTL power models for soft macros, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.880-887, 12/1/2001
	Axel Reimer , Arne Schulz , Wolfgang Nebel, Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designs, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
	A. Stammermann , D. Helms , M. Schulte , A. Schulz , W. Nebel, Binding, Allocation and Floorplanning in Low Power High-Level Synthesis, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.544, November 09-13, 2003
	Felipe Klein , G. Araujo , Rodolfo Azevedo , Roberto Leao , Luiz C. V. dos Santos, A multi-model power estimation engine for accuracy optimization, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA