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Resource usage models for instruction scheduling: two new models and a classification
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Source International Conference on Supercomputing archive
Proceedings of the 13th international conference on Supercomputing table of contents
Rhodes, Greece
Pages: 417 - 424  
Year of Publication: 1999
ISBN:1-58113-164-X
Authors
V. Janaki Ramanan  Supercomputer Education and Research Centre, Indian Institute of Science, Bangalore 560 012, India
R. Govindarajan  Supercomputer Education and Research Centre, Department of Computer Science and Automation, Indian Institute of Science, Bangalore 560 012, India
Sponsor
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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J. A. Fisher. Trace scheduling: A technique for global microcode compaction. IEEE Trans. on Computers, 7(30):478- 490~ July 1981.
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P.Y-T. Hsu. Design of the r-8000 microprocessor. Technical report, MIPS Technologies Inc., Mountain View, CA, June 1994.
 
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P. M. Kogge. The Architecture of Pipelined Computers. McGraw-Hill Book Co., New York, NY, 1981.
 
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M. S. Lain. Instruction scheduling for superscalar architectures. Annual Review of Comp. Sci., 4:173-201, 1990.
 
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Collaborative Colleagues:
V. Janaki Ramanan: colleagues
R. Govindarajan: colleagues