Classifying load and store instructions for memory renaming

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Classifying load and store instructions for memory renaming

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International Conference on Supercomputing archive
Proceedings of the 13th international conference on Supercomputing table of contents

Rhodes, Greece

Pages: 399 - 407

Year of Publication: 1999

ISBN:1-58113-164-X

Authors

Glenn Reinman	Department of Computer Science and Engineering, University of California, San Diego
Brad Calder	Department of Computer Science and Engineering, University of California, San Diego
Dean Tullsen	Department of Computer Science and Engineering, University of California, San Diego
Gary Tyson	Electrical Engineering and Computer Science Department, University of Michigan
Todd Austin	Microcomputer Research Labs, Intel Corporation

Sponsor

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 16, Citation Count: 6

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	D.C. Burger and T.M. Austin. The simplescalar tool set, version 2.0. Technical Report CS-TR-97-1342, University of Wisconsin, Madison, June 1997.
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	3	B. Calder, P. Feller, and A. Eustace. Value prediction and optimization. Journal of Instruction Level Parallelism, 1(1), March 1999.
	4	Brad Calder , Glenn Reinman , Dean M. Tullsen, Selective value prediction, Proceedings of the 26th annual international symposium on Computer architecture, p.64-74, May 01-04, 1999, Atlanta, Georgia, United States
	5	Thomas M. Conte , Kishore N. Menezes , Patrick M. Mills , Burzin A. Patel, Optimization of instruction fetch mechanisms for high issue rates, Proceedings of the 22nd annual international symposium on Computer architecture, p.333-344, June 22-24, 1995, S. Margherita Ligure, Italy
	6	Manoj Franklin , Gurindar S. Sohi, ARB: A Hardware Mechanism for Dynamic Reordering of Memory References, IEEE Transactions on Computers, v.45 n.5, p.552-571, May 1996 [doi>10.1109/12.509907]
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	15	M. Moudgill and l. H. Moreno. Run-time detection and recovery from incorrectly reordered memory operations. Technical Report RC 20857, IBM Research Report, May 1997,
	16	Glenn Reinman , Brad Calder, Predictive techniques for aggressive load speculation, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.127-137, November 1998, Dallas, Texas, United States
	17	Eric Rotenberg , Steve Bennett , James E. Smith, Trace cache: a low latency approach to high bandwidth instruction fetching, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.24-35, December 02-04, 1996, Paris, France
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CITED BY 6

	Daniel Ortega , Mateo Valero , Eduard Ayguadé, A novel renaming mechanism that boosts software prefetching, Proceedings of the 15th international conference on Supercomputing, p.501-510, June 2001, Sorrento, Italy
	Craig B. Zilles , Gurindar S. Sohi, Understanding the backward slices of performance degrading instructions, ACM SIGARCH Computer Architecture News, v.28 n.2, p.172-181, May 2000
	Gary S. Tyson , Todd M. Austin, Memory Renaming: Fast, Early and Accurate Processing of Memory Communication, International Journal of Parallel Programming, v.27 n.5, p.357-380, Oct. 1999
	Daniel Ortega , Mateo Valero , Eduard Ayguadé, Dynamic memory instruction bypassing, International Journal of Parallel Programming, v.32 n.3, p.199-224, June 2004
	Changpeng Fang , Steve Carr , Soner Önder , Zhenlin Wang, Feedback-directed memory disambiguation through store distance analysis, Proceedings of the 20th annual international conference on Supercomputing, June 28-July 01, 2006, Cairns, Queensland, Australia
	Alexandru Nicolau , Guangqiang Li , Alexander V. Veidenbaum , Arun Kejariwal, Synchronization optimizations for efficient execution on multi-cores, Proceedings of the 23rd international conference on Supercomputing, June 08-12, 2009, Yorktown Heights, NY, USA