|
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
D. Psaltis and F. Mok, "Holographic Memories," Scientific American, Nov 1995, Vol. 273, No. 5, pp. 70-76.
|
| |
2
|
I. Redmond, R. Linke, E. Chuang, and D. Psaltis, "Holographic Data Storage in a DX-Center Material," Optics Letters 22:(15), pp. 1189-1191, Aug 1, 1997.
|
| |
3
|
|
| |
4
|
J. Cohen, "Mix of Technologies Spurs Future Supercomputer," NASA Insights, July 1998, pp. 2-11.
|
| |
5
|
T. Sterling, "In Pursuit of a Quadrillion Operations per Second," NASA Insights, April 1998, pp. 8-11.
|
| |
6
|
M. Dorojevets, P. Bunyk, D. Zinoviev, and K. Likharev, "Petaflops RSFQ System Design, "IEEE Transaction Applied Superconductivity, in press.
|
| |
7
|
K. Likharev, "Ultrafast Superconductor Digital Electronics: RSFQ Technology Roadmap," Czeehoslovok J. Physics, vol. 46, Supplement S6, 1996.
|
| |
8
|
|
| |
9
|
K. Likharev, "Superconductors Speed Up Computation," Physics World, May 1997, pp. 39-43.
|
| |
10
|
K. Likharev, "RSFQ Digital Electronics: Achievements, Prospects, and Problems (Invited)," Appl. Superconductivity Conf., Palm Desert, CA, Sept 13-18, 1998.
|
| |
11
|
L. Abelson, Q. Herr, G. Kerber, M. Leung, and T. Tighe, "Full Scale Integration of Superconductor Electronics for Petafiops Computing "2nd Conf. for Enabling Technologies for Petaflops Computing, Santa Barbara, Feb 1999.
|
| |
12
|
K. Bergman, "Ultra-High Speed Optical LANs," Conference on Optical Fiber Communications (0FC'98), Workshop on LANs and WANs, San Jose, CA, Feb 1998.
|
| |
13
|
B. Smith, "Alternatives and Imperatives for Optical Interconnects in High Performance Computers," OSA Spring Topical Meeting on Optical Computing, Lake Tahoe, CA, Session JTuC I, March 18, 1997.
|
| |
14
|
K. Gaj, Q. Herr, V. Adler, A. Krasnicwski, E. Friedman, and M. Feldman, "Tools for the Computer-Aided Design of Multi-Gigahertz Superconducting Digital Circuits," HTMT TechNote, No. 26, submitted for ext. publication, Oct 1998.
|
| |
15
|
|
| |
16
|
P. Kogge, J. Broekman, T. Sterling, and G. Gao, "Processing in Memory: Chips to Petafiops," ICSA Workshop on Mixing Logic and DRAM, June 1, 1997.
|
| |
17
|
G. Gao, K. Theobald, A. Marquez, and T. Sterling, "The HTMT Program Execution Model," University of Delaware, Department of Electrical and Computer Engineering, CAPSL Technical Memo No. 9, July 18, 1997.
|
CITED BY 7
|
|
George S. Almasi , Călin Caşcaval , José G. Castaños , Monty Denneau , Wilm Donath , Maria Eleftheriou , Mark Giampapa , Howard Ho , Derek Lieber , José E. Moreira , Dennis Newns , Marc Snir , Henry S. Warren, Jr., Demonstrating the Scalability of a Molecular Dynamics Application on a Petaflops Computer, International Journal of Parallel Programming, v.30 n.4, p.317-351, August 2002
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Jay B. Brockman , Shyamkumar Thoziyoor , Shannon K. Kuntz , Peter M. Kogge, A low cost, multithreaded processing-in-memory system, Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture, p.16-22, June 20-20, 2004, Munich, Germany
|
|
|
|
|