Reducing cache misses using hardware and software page placement

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Reducing cache misses using hardware and software page placement

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International Conference on Supercomputing archive
Proceedings of the 13th international conference on Supercomputing table of contents

Rhodes, Greece

Pages: 155 - 164

Year of Publication: 1999

ISBN:1-58113-164-X

Authors

Timothy Sherwood	Department of Computer Science and Engineering, University of California, San Diego
Brad Calder	Department of Computer Science and Engineering, University of California, San Diego
Joel Emer	Alpha Development Group, Compaq Computer Corporation

Sponsor

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 39, Citation Count: 13

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Anant Agarwal , Stephen D. Pudar, Column-associative caches: a technique for reducing the miss rate of direct-mapped caches, ACM SIGARCH Computer Architecture News, v.21 n.2, p.179-190, May 1993
	2	Brian N. Bershad , Dennis Lee , Theodore H. Romer , J. Bradley Chen, Avoiding conflict misses dynamically in large direct-mapped caches, Proceedings of the sixth international conference on Architectural support for programming languages and operating systems, p.158-170, October 05-07, 1994, San Jose, California, United States
	3	Edouard Bugnion , Jennifer M. Anderson , Todd C. Mowry , Mendel Rosenblum , Monica S. Lam, Compiler-directed page coloring for multiprocessors, Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, p.244-255, October 01-04, 1996, Cambridge, Massachusetts, United States
	4	D.C. Burger and T.M. Austin. The simplescalar tool set, version 2.0. Technical Report CS-TR-97-1342, University of Wisconsin, Madison, June 1997.
	5	B. Calder , D. Grunwald , J. Emer, Predictive sequential associative cache, Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture, p.244, February 03-07, 1996
	6	Brad Calder , Chandra Krintz , Simmi John , Todd Austin, Cache-conscious data placement, Proceedings of the eighth international conference on Architectural support for programming languages and operating systems, p.139-149, October 02-07, 1998, San Jose, California, United States
	7	Steve Carr , Kathryn S. McKinley , Chau-Wen Tseng, Compiler optimizations for improving data locality, Proceedings of the sixth international conference on Architectural support for programming languages and operating systems, p.252-262, October 05-07, 1994, San Jose, California, United States
	8	J. Carter , W. Hsieh , L. Stoller , M. Swanson , L. Zhang , E. Brunvand , A. Davis , C.-C. Kuo , R. Kuramkote , M. Parker , L. Schaelicke , T. Tateyama, Impulse: Building a Smarter Memory Controller, Proceedings of the 5th International Symposium on High Performance Computer Architecture, p.70, January 09-12, 1999
	9	Thomas M. Conte , Kishore N. Menezes , Patrick M. Mills , Burzin A. Patel, Optimization of instruction fetch mechanisms for high issue rates, Proceedings of the 22nd annual international symposium on Computer architecture, p.333-344, June 22-24, 1995, S. Margherita Ligure, Italy
	10	D. R. Engler , M. F. Kaashoek , J. O'Toole, Jr., Exokernel: an operating system architecture for application-level resource management, Proceedings of the fifteenth ACM symposium on Operating systems principles, p.251-266, December 03-06, 1995, Copper Mountain, Colorado, United States
	11	K. Ghose and M.B. Kamble. Energy eft%lent cache organizations for superscalar processors. In Power-Driven Microarchitecture Workshop, June 1998.
	12	Nikolas Gloy , Trevor Blackwell , Michael D. Smith , Brad Calder, Procedure placement using temporal ordering information, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.303-313, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	13	Lance Hammond , Basem A. Nayfeh , Kunle Olukotun, A Single-Chip Multiprocessor, Computer, v.30 n.9, p.79-85, September 1997 [doi>10.1109/2.612253]
	14	Kieran Harty , David R. Cheriton, Application-controlled physical memory using external page-cache management, Proceedings of the fifth international conference on Architectural support for programming languages and operating systems, p.187-197, October 12-15, 1992, Boston, Massachusetts, United States
	15	Amir H. Hashemi , David R. Kaeli , Brad Calder, Efficient procedure mapping using cache line coloring, Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation, p.171-182, June 16-18, 1997, Las Vegas, Nevada, United States
	16	W. W. Hwu , P. P. Chang, Achieving high instruction cache performance with an optimizing compiler, Proceedings of the 16th annual international symposium on Computer architecture, p.242-251, April 1989, Jerusalem, Israel
	17	Bruce L. Jacob , Trevor N. Mudge, A look at several memory management units, TLB-refill mechanisms, and page table organizations, Proceedings of the eighth international conference on Architectural support for programming languages and operating systems, p.295-306, October 02-07, 1998, San Jose, California, United States
	18	Teresa L. Johnson , Matthew C. Merten , Wen-Mei W. Hwu, Run-time spatial locality detection and optimization, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.57-64, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	19	Norman P. Jouppi, Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, Proceedings of the 17th annual international symposium on Computer Architecture, p.364-373, May 28-31, 1990, Seattle, Washington, United States
	20	Milind B. Kamble , Kanad Ghose, Analytical energy dissipation models for low-power caches, Proceedings of the 1997 international symposium on Low power electronics and design, p.143-148, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263310]
	21	R. E. Kessler , Mark D. Hill, Page placement algorithms for large real-indexed caches, ACM Transactions on Computer Systems (TOCS), v.10 n.4, p.338-359, Nov. 1992 [doi>10.1145/138873.138876]
	22	R. E. Kessler. Analysis of Multi-Megabyte Secondary CPU Cache Memories. TR 1032, Computer Sciences Department, UW-Madison, Madison, WI, July 1991.
	23	R. E. Kessler , R. Jooss , A. Lebeck , M. D. Hill, Inexpensive implementations of set-associativity, ACM SIGARCH Computer Architecture News, v.17 n.3, p.131-139, June 1989
	24	S. McFarling, Program optimization for instruction caches, Proceedings of the third international conference on Architectural support for programming languages and operating systems, p.183-191, April 03-06, 1989, Boston, Massachusetts, United States
	25	Kathryn S. McKinley , Steve Carr , Chau-Wen Tseng, Improving data locality with loop transformations, ACM Transactions on Programming Languages and Systems (TOPLAS), v.18 n.4, p.424-453, July 1996 [doi>10.1145/233561.233564]
	26	Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau, Memory data organization for improved cache performance in embedded processor applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.4, p.384-409, Oct. 1997 [doi>10.1145/268424.268464]
	27	Jih-Kwon Peir , Yongjoon Lee , Windsor W. Hsu, Capturing dynamic memory reference behavior with adaptive cache topology, Proceedings of the eighth international conference on Architectural support for programming languages and operating systems, p.240-250, October 02-07, 1998, San Jose, California, United States
	28	Karl Pettis , Robert C. Hansen, Profile guided code positioning, ACM SIGPLAN Notices, v.25 n.6, p.16-27, Jun. 1990
	29	Gabriel Rivera , Chau-Wen Tseng, Data transformations for eliminating conflict misses, Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation, p.38-49, June 17-19, 1998, Montreal, Quebec, Canada
	30	T. Romer, D. Lee, B. Bershad, and J.B Chen. Dynamic page mapping policies for cache conflict resolution on standard hardware. In Proceedings of the 1st Symposium on Operatingy Systems Design and Implemenation, pages 255-266, November 1994.
	31	Amitabh Srivastava , Alan Eustace, ATOM: a system for building customized program analysis tools, Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation, p.196-205, June 20-24, 1994, Orlando, Florida, United States
	32	Dean M. Tullsen , Susan J. Eggers , Henry M. Levy, Simultaneous multithreading: maximizing on-chip parallelism, Proceedings of the 22nd annual international symposium on Computer architecture, p.392-403, June 22-24, 1995, S. Margherita Ligure, Italy
	33	Gary Tyson , Matthew Farrens , John Matthews , Andrew R. Pleszkun, Managing data caches using selective cache line replacement, International Journal of Parallel Programming, v.25 n.3, p.213-242, June 1997 [doi>10.1007/BF02700036]
	34	S. J.E. Wilton and N. P. Jouppi. An enhanced access and cycle time model for on-chip caches. Teeh report 93/5, DEC Western Research Lab, 1994.
	35	Yoji Yamada , John Gyllenhall , Grant Haab , Wen-mei Hwu, Data relocation and prefetching for programs with large data sets, Proceedings of the 27th annual international symposium on Microarchitecture, p.118-127, November 30-December 02, 1994, San Jose, California, United States [doi>10.1145/192724.192740]

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	Erik G. Hallnor , Steven K. Reinhardt, A fully associative software-managed cache design, ACM SIGARCH Computer Architecture News, v.28 n.2, p.107-116, May 2000
	Carl A. Waldspurger, Memory resource management in VMware ESX server, ACM SIGOPS Operating Systems Review, v.36 n.SI, Winter 2002
	Jayaprakash Pisharath , Alok Choudhary, An integrated approach to reducing power dissipation in memory hierarchies, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
	Carl A. Waldspurger, Memory resource management in VMware ESX server, Proceedings of the 5th symposium on Operating systems design and implementation Due to copyright restrictions we are not able to make the PDFs for this conference available for downloading , December 09-11, 2002, Boston, Massachusetts
	Rakesh Kumar , Dean M. Tullsen, Compiling for instruction cache performance on a multithreaded architecture, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Lei Jin , Hyunjin Lee , Sangyeun Cho, A flexible data to L2 cache mapping approach for future multicore processors, Proceedings of the 2006 workshop on Memory system performance and correctness, October 22-22, 2006, San Jose, California
	Michal Marko , A. Wayne Madison, Cache conflict resolution through detection, analysis and dynamic remapping of active pages, Proceedings of the 38th annual on Southeast regional conference, April 07-08, 2000, Clemson, South Carolina
	Rajiv Ravindran , Michael Chu , Scott Mahlke, Compiler-managed partitioned data caches for low power, ACM SIGPLAN Notices, v.42 n.7, July 2007
	Sangyeun Cho , Lei Jin, Managing Distributed, Shared L2 Caches through OS-Level Page Allocation, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.455-468, December 09-13, 2006
	Reza Azimi , David K. Tam , Livio Soares , Michael Stumm, Enhancing operating system support for multicore processors by using hardware performance monitoring, ACM SIGOPS Operating Systems Review, v.43 n.2, April 2009
	Livio Soares , David Tam , Michael Stumm, Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.258-269, November 08-12, 2008
	Xiao Zhang , Sandhya Dwarkadas , Kai Shen, Towards practical page coloring-based multicore cache management, Proceedings of the fourth ACM european conference on Computer systems, April 01-03, 2009, Nuremberg, Germany
	Nikos Hardavellas , Michael Ferdman , Babak Falsafi , Anastasia Ailamaki, Reactive NUCA: near-optimal block placement and replication in distributed caches, ACM SIGARCH Computer Architecture News, v.37 n.3, June 2009