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CACHET: an adaptive cache coherence protocol for distributed shared-memory systems

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International Conference on Supercomputing archive
Proceedings of the 13th international conference on Supercomputing table of contents

Rhodes, Greece

Pages: 135 - 144

Year of Publication: 1999

ISBN:1-58113-164-X

Authors

Xiaowei Shen	Laboratory for Computer Science, Massachusetts Institute of Technology
Arvind	Laboratory for Computer Science, Massachusetts Institute of Technology
Larry Rudolph	Laboratory for Computer Science, Massachusetts Institute of Technology

Sponsor

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 16, Citation Count: 6

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	John K. Bennett , John B. Carter , Willy Zwaenepoel, Adaptive software cache management for distributed shared memory architectures, Proceedings of the 17th annual international symposium on Computer Architecture, p.125-134, May 28-31, 1990, Seattle, Washington, United States
	2	Satish Chandra , Brad Richards , James R. Larus, Teapot: language support for writing memory coherence protocols, Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation, p.237-248, May 21-24, 1996, Philadelphia, Pennsylvania, United States
	3	Alan L. Cox , Robert J. Fowler, Adaptive cache coherency for detecting migratory shared data, Proceedings of the 20th annual international symposium on Computer architecture, p.98-108, May 16-19, 1993, San Diego, California, United States
	4	S. J. Eggers , R. H. Katz, Evaluating the performance of four snooping cache coherency protocols, Proceedings of the 16th annual international symposium on Computer architecture, p.2-15, April 1989, Jerusalem, Israel
	5	Babak Falsafi , Alvin R. Lebeck , Steven K. Reinhardt , Ioannis Schoinas , Mark D. Hill , James R. Larus , Anne Rogers , David A. Wood, Application-specific protocols for user-level shared memory, Proceedings of the 1994 conference on Supercomputing, p.380-389, December 1994, Washington, D.C., United States
	6	Kourosh Gharachorloo , Daniel Lenoski , James Laudon , Phillip Gibbons , Anoop Gupta , John Hennessy, Memory consistency and event ordering in scalable shared-memory multiprocessors, Proceedings of the 17th annual international symposium on Computer Architecture, p.15-26, May 28-31, 1990, Seattle, Washington, United States
	7	L. Lamport. How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs. IEEE Transactions on Computers, C-28(9):690-691, Sept. 1979.
	8	Shubhendu S. Mukherjee , Mark D. Hill, Using prediction to accelerate coherence protocols, Proceedings of the 25th annual international symposium on Computer architecture, p.179-190, June 27-July 02, 1998, Barcelona, Spain
	9	X. Shen and Arvind. Specification of Memory Models and Design of Provably Correct Cache Coherence Protocols. CSG Memo 398, Laboratory for Computer Science, MIT, June 1997.
	10	Xiaowei Shen , Arvind , Larry Rudolph, Commit-reconcile & fences (CRF): a new memory model for architects and compiler writers, Proceedings of the 26th annual international symposium on Computer architecture, p.150-161, May 01-04, 1999, Atlanta, Georgia, United States
	11	Per Stenström , Mats Brorsson , Lars Sandberg, An adaptive cache coherence protocol optimized for migratory sharing, Proceedings of the 20th annual international symposium on Computer architecture, p.109-118, May 16-19, 1993, San Diego, California, United States
	12	W. Weber , A. Gupta, Analysis of cache invalidation patterns in multiprocessors, Proceedings of the third international conference on Architectural support for programming languages and operating systems, p.243-256, April 03-06, 1989, Boston, Massachusetts, United States

CITED BY 6

	Arvind , Xiaowei Shen, Using Term Rewriting Systems to Design and Verify Processors, IEEE Micro, v.19 n.3, p.36-46, May 1999
	Milo M. K. Martin , Mark D. Hill , David A. Wood, Token coherence: decoupling performance and correctness, ACM SIGARCH Computer Architecture News, v.31 n.2, May 2003
	M. Ayala-Rincón , C. H. Llanos , R. P. Jacobi , R. W. Hartenstein, Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.2, p.251-281, April 2006
	Noel Eisley , Li-Shiuan Peh , Li Shang, In-Network Cache Coherence, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.321-332, December 09-13, 2006
	Edya Ladan-Mozes , Charles E. Leiserson, A consistency architecture for hierarchical shared caches, Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures, June 14-16, 2008, Munich, Germany
	Evgeny Bolotin , Zvika Guz , Israel Cidon , Ran Ginosar , Avinoam Kolodny, The Power of Priority: NoC Based Distributed Cache Coherency, Proceedings of the First International Symposium on Networks-on-Chip, p.117-126, May 07-09, 2007