Reducing branch misprediction penalties via dynamic control independence detection

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Reducing branch misprediction penalties via dynamic control independence detection

Full text

Pdf (3.47 MB)

Source

International Conference on Supercomputing archive
Proceedings of the 13th international conference on Supercomputing table of contents

Rhodes, Greece

Pages: 109 - 118

Year of Publication: 1999

ISBN:1-58113-164-X

Authors

Yuan Chou	Carnegie Mellon Microarchitecture Research Team (CMuART), Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA
Jason Fung	Intel Corp. and Carnegie Mellon Microarchitecture Research Team (CMuART), Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA
John Paul Shen	Carnegie Mellon Microarchitecture Research Team (CMuART), Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA

Sponsor

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 25, Citation Count: 14

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/305138.305175 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. johnson, Superscalar Processor Design, Prentice-Hall, pp 110, 1990.
	2	Dirk Grunwald , Artur Klauser , Srilatha Manne , Andrew Pleszkun, Confidence estimation for speculation control, Proceedings of the 25th annual international symposium on Computer architecture, p.122-131, June 27-July 02, 1998, Barcelona, Spain
	3	Erik Jacobsen , Eric Rotenberg , J. E. Smith, Assigning confidence to conditional branch predictions, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.142-152, December 02-04, 1996, Paris, France
	4	Amitabh Srivastava , Alan Eustace, ATOM: a system for building customized program analysis tools, Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation, p.196-205, June 20-24, 1994, Orlando, Florida, United States
	5	Alpha Architecture Handbook, Digital Equipment Corporation, 1992.
	6	Yuan Chou, Jason Fung, and John P. Shen, "Reducing Branch Misprediction Penalties Via Dynamic Control Independence Detection," CMuART Tech. Report, Carnegie Mellon Univ., Mar. 1999
	7	Scott McFarling, "Combining Branch Predictors," Technical Report TN-36, DEC-WRL, June 1993.
	8	IBM Microelectronics Division, PowerPC 604 RISC Microprocessor User's Manual, 1994.
	9	Linley Gwennap, "Intel's P6 Uses Deeoupled Supersealar Design," in Microprocessor Report, Vol, 9, Issue 2, Feb. 1995.
	10	P Y Hsu, Highly concurrent scalar processing, University of Illinois, Department of Computer Science, Urbana, IL, 1986
	11	David I. August , Wen-mei W. Hwu , Scott A. Mahlke, A framework for balancing control flow and predication, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.92-103, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	12	Linley Gwennap, "Design Concepts for Merced," in Microprocessor Report, Vol. 11, Issue 3, Mar. 1997.
	13	Timothy Heil and James Smith, "Selective Dual Path Execution,'' University of Wisconsin-Madison, Nov. 1996.
	14	Gary Tyson, Kelsey Lick, and Matthew Fattens, "Limited Dual Path Execution," CSE-TR 346-97, Univ. of Michigan, 1997.
	15	Augustus K. Uht , Vijay Sindagi , Kelley Hall, Disjoint eager execution: an optimal form of speculative execution, Proceedings of the 28th annual international symposium on Microarchitecture, p.313-325, November 29-December 01, 1995, Ann Arbor, Michigan, United States
	16	Artur Klauser , Abhijit Paithankar , Dirk Grunwald, Selective eager execution on the PolyPath architecture, Proceedings of the 25th annual international symposium on Computer architecture, p.250-259, June 27-July 02, 1998, Barcelona, Spain
	17	Steven Wallace , Brad Calder , Dean M. Tullsen, Threaded multiple path execution, Proceedings of the 25th annual international symposium on Computer architecture, p.238-249, June 27-July 02, 1998, Barcelona, Spain
	18	Monica S. Lam , Robert P. Wilson, Limits of control flow on parallelism, Proceedings of the 19th annual international symposium on Computer architecture, p.46-57, May 19-21, 1992, Queensland, Australia
	19	Eric Rotenberg , Quinn Jacobson , Yiannakis Sazeides , Jim Smith, Trace processors, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.138-148, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	20	E. Rotenberg , Q. Jacobson , J. Smith, A Study of Control Independence in Superscalar Processors, Proceedings of the 5th International Symposium on High Performance Computer Architecture, p.115, January 09-12, 1999
	21	Avinash Sodani , Gurindar S. Sohi, Dynamic instruction reuse, Proceedings of the 24th annual international symposium on Computer architecture, p.194-205, June 01-04, 1997, Denver, Colorado, United States

CITED BY 14

	Peng Zhou , Soner Õnder, Improving single-thread performance with fine-grain state maintenance, Proceedings of the 2008 conference on Computing frontiers, May 05-07, 2008, Ischia, Italy
	Eric Rotenberg , Jim Smith, Control independence in trace processors, Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.4-15, November 16-18, 1999, Haifa, Israel
	Amir Roth , Gurindar S. Sohi, Register integration: a simple and efficient implementation of squash reuse, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.223-234, December 2000, Monterey, California, United States
	Marc L. Corliss , E. Christopher Lewis , Amir Roth, DISE: a programmable macro engine for customizing applications, ACM SIGARCH Computer Architecture News, v.31 n.2, May 2003
	Vlad Petric , Anne Bracy , Amir Roth, Three extensions to register integration, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Chen-Yong Cher , T. N. Vijaykumar, Skipper: a microarchitecture for exploiting control-flow independence, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
	Neil Vachharajani , Matthew Iyer , Chinmay Ashok , Manish Vachharajani , David I. August , Daniel Connors, Chip multi-processor scalability for single-threaded applications, ACM SIGARCH Computer Architecture News, v.33 n.4, November 2005
	Jamison D. Collins , Dean M. Tullsen , Hong Wang, Control Flow Optimization Via Dynamic Reconvergence Prediction, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.129-140, December 04-08, 2004, Portland, Oregon
	Patrick Akl , Andreas Moshovos, BranchTap: improving performance with very few checkpoints through adaptive speculation control, Proceedings of the 20th annual international conference on Supercomputing, June 28-July 01, 2006, Cairns, Queensland, Australia
	Andrew D. Hilton , Amir Roth, Ginger: control independence using tag rewriting, ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
	Ahmed S. Al-Zawawi , Vimal K. Reddy , Eric Rotenberg , Haitham H. Akkary, Transparent control independence (TCI), ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
	Hyesoon Kim , Onur Mutlu , Jared Stark , Yale N. Patt, Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution, Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, p.43-54, November 12-16, 2005, Barcelona, Spain
	Hyesoon Kim , Jose A. Joao , Onur Mutlu , Yale N. Patt, Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.53-64, December 09-13, 2006
	Amit Golander , Shlomo Weiss, Hiding the misprediction penalty of a resource-efficient high-performance processor, ACM Transactions on Architecture and Code Optimization (TACO), v.4 n.4, p.1-32, January 2008