A locality sensitive multi-module cache with explicit management

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A locality sensitive multi-module cache with explicit management

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International Conference on Supercomputing archive
Proceedings of the 13th international conference on Supercomputing table of contents

Rhodes, Greece

Pages: 51 - 59

Year of Publication: 1999

ISBN:1-58113-164-X

Authors

Jesús Sánchez	Department of Computer Architecture, Universitat Politècnica de Catalunya, Barcelona, Spain
Antonio González	Department of Computer Architecture, Universitat Politècnica de Catalunya, Barcelona, Spain

Sponsor

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 17, Citation Count: 7

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	E. Ayguad6, C. Barrado, A. Gonzfilez, J. Labarta, D. L6pez, S. Moreno, D. Padua, E Reig, Q. Riera and M. Valero, "ICTI- NEO: a Tool for Research on ILP', in Supercomputing'96 Conf. (SC'96), Research Exhibit 'Polaris at Work', 1996
	2	Doug Burger , James R. Goodman , Alain Kägi, Memory bandwidth limitations of future microprocessors, Proceedings of the 23rd annual international symposium on Computer architecture, p.78-89, May 22-24, 1996, Philadelphia, Pennsylvania, United States
	3	Steve Carr , Kathryn S. McKinley , Chau-Wen Tseng, Compiler optimizations for improving data locality, Proceedings of the sixth international conference on Architectural support for programming languages and operating systems, p.252-262, October 05-07, 1994, San Jose, California, United States
	4	K.K. Chart, C.C. Hay, J.R. Keller, G.P. Kurpanek, F.X. Schureacher and J. Zheng, "Design of the HP PA 7200 CPU", Hewlett-Packard Journal, Feb. 1996
	5	Zarka Cvetanovic , Dileep Bhandarkar, Performance Characterization of the Alpha 21164 Microprocessor Using TP and SPEC Workloads, Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture, p.270, February 03-07, 1996
	6	Dennis Gannon , William Jalby , Kyle Gallivan, Strategies for cache and local memory management by global program transformation, Journal of Parallel and Distributed Computing, v.5 n.5, p.587-616, October 1988 [doi>10.1016/0743-7315(88)90014-7]
	7	Antonio González , Carlos Aliagas , Mateo Valero, A data cache with multiple caching strategies tuned to different types of locality, Proceedings of the 9th international conference on Supercomputing, p.338-347, July 03-07, 1995, Barcelona, Spain [doi>10.1145/224538.224622]
	8	S. Hadjiyannis, M. Tomasko and W. Najjar, "An Evaluation of Split Scalar/Array Caches", Technical Report CS-TR-97- 104, CS Department, Colorado State University, Jan. 1997
	9	John L. Hennessy , David A. Patterson, Computer architecture (2nd ed.): a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1996
	10	Andrew S. Huang , John P. Shen, A limit study of local memory requirements using value reuse profiles, Proceedings of the 28th annual international symposium on Microarchitecture, p.71-81, November 29-December 01, 1995, Ann Arbor, Michigan, United States
	11	Teresa L. Johnson , Wen-mei W. Hwu, Run-time adaptive cache hierarchy management via reference analysis, Proceedings of the 24th annual international symposium on Computer architecture, p.315-326, June 01-04, 1997, Denver, Colorado, United States
	12	Norman P. Jouppi, Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, Proceedings of the 17th annual international symposium on Computer Architecture, p.364-373, May 28-31, 1990, Seattle, Washington, United States
	13	V. Kathail, M. Schlansker and B. Rau, "HPLabs PlayDoh Architecture Specification: Version 1.0", Technical Report HPL-93-80, Hewlett-Packard Labs., March ! 994
	14	V. Milutinovic, B. Markovic, M. Tomasevic and M. Tremblay, "The Split Temporal/Spatial Cache: Initial Performance Analysis", in Procs. of SClzzL-5 Workshop, pp. 63-70, March 1996
	15	S. Palacharla , R. E. Kessler, Evaluating stream buffers as a secondary cache replacement, Proceedings of the 21ST annual international symposium on Computer architecture, p.24-33, April 18-21, 1994, Chicago, Illinois, United States
	16	J.A. Rivers and E.g. Davidson, "Reducing Conflicts in Direct- Mapped Caches with Temporality-Based Design", in Procs. of 1996 Int. Conf. on Parallel Processing (ICPP'96), pp. 93- 103, Dec. 1996
	17	Jude A. Rivers , Edward S. Tam , Gary S. Tyson , Edward S. Davidson , Matt Farrens, Utilizing reuse information in data cache management, Proceedings of the 12th international conference on Supercomputing, p.449-456, July 1998, Melbourne, Australia [doi>10.1145/277830.277941]
	18	F. Jesus Sanchez , Antonio Gonzalez , Mateo Valero, Static Locality Analysis for Cache Management, Proceedings of the 1997 International Conference on Parallel Architectures and Compilation Techniques, p.261, November 11-15, 1997
	19	Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982 [doi>10.1145/356887.356892]
	20	Amitabh Srivastava , Alan Eustace, ATOM: a system for building customized program analysis tools, Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation, p.196-205, June 20-24, 1994, Orlando, Florida, United States
	21	Janice M. Stone , Robert P. Fitzgerald, Storage in the PowerPC, IEEE Micro, v.15 n.2, p.50-58, April 1995 [doi>10.1109/40.372352]
	22	Gary Tyson , Matthew Farrens , John Matthews , Andrew R. Pleszkun, A modified approach to data cache management, Proceedings of the 28th annual international symposium on Microarchitecture, p.93-103, November 29-December 01, 1995, Ann Arbor, Michigan, United States
	23	Michael E. Wolf , Monica S. Lam, A data locality optimizing algorithm, Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, p.30-44, June 24-28, 1991, Toronto, Ontario, Canada

CITED BY 7

	Julio Sahuquillo , Ana Pont, Splitting the Data Cache: A Survey, IEEE Concurrency, v.8 n.3, p.30-35, July 2000
	Jesús Sánchez , Antonio González, Analyzing Data Locality in Numeric Applications, IEEE Micro, v.20 n.4, p.58-66, July 2000
	Kristof Beyls , Erik H. D'Hollander, Generating cache hints for improved program efficiency, Journal of Systems Architecture: the EUROMICRO Journal, v.51 n.4, p.223-250, April 2005
	S. Bartolini , C. A. Prete, Optimizing instruction cache performance of embedded systems, ACM Transactions on Embedded Computing Systems (TECS), v.4 n.4, p.934-965, November 2005
	J. Sahuquillo , S. Petit , A. Pont , V. Milutinović, Exploring the performance of split data cache schemes on superscalar processors and symmetric multiprocessors, Journal of Systems Architecture: the EUROMICRO Journal, v.51 n.8, p.451-469, August 2005
	S. Bartolini , C. A. Prete, A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applications, ACM SIGARCH Computer Architecture News, v.32 n.3, p.70-77, June 2004
	Rajiv Ravindran , Michael Chu , Scott Mahlke, Compiler-managed partitioned data caches for low power, ACM SIGPLAN Notices, v.42 n.7, July 2007