Adding a vector unit to a superscalar processor

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Adding a vector unit to a superscalar processor

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International Conference on Supercomputing archive
Proceedings of the 13th international conference on Supercomputing table of contents

Rhodes, Greece

Pages: 1 - 10

Year of Publication: 1999

ISBN:1-58113-164-X

Authors

Francisca Quintana	Departamento de Informatica y Sistemas, Universidad de Las Palmas de Gran Canaria-Las Palmas, Spain
Jesus Corbal	Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya-Barcelona, Spain
Roger Espasa	Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya-Barcelona, Spain
Mateo Valero	Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya-Barcelona, Spain

Sponsor

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 24, Citation Count: 10

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Subbarao Palacharla , Norman P. Jouppi , J. E. Smith, Complexity-effective superscalar processors, Proceedings of the 24th annual international symposium on Computer architecture, p.206-218, June 01-04, 1997, Denver, Colorado, United States
	2	Eric Rotenberg , Steve Bennett , James E. Smith, Trace cache: a low latency approach to high bandwidth instruction fetching, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.24-35, December 02-04, 1996, Paris, France
	3	Thomas M. Conte , Kishore N. Menezes , Patrick M. Mills , Burzin A. Patel, Optimization of instruction fetch mechanisms for high issue rates, Proceedings of the 22nd annual international symposium on Computer architecture, p.333-344, June 22-24, 1995, S. Margherita Ligure, Italy
	4	Alex Peleg , Uri Weiser, MMX Technology Extension to the Intel Architecture, IEEE Micro, v.16 n.4, p.42-50, August 1996 [doi>10.1109/40.526924]
	5	Marc Tremblay , J. Michael O'Connor , Venkatesh Narayanan , Liang He, VIS Speeds New Media Processing, IEEE Micro, v.16 n.4, p.10-20, August 1996 [doi>10.1109/40.526921]
	6	Altivec Technology. Technical Report http://www.mot.com/SPS/PowerrC/AltiVec/, Motorola, Inc., 1998.
	7	Corinna G. Lee , Derek J. DeVries, Initial results on the performance and cost of vector microprocessors, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.171-182, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	8	Corinna G. Lee , Mark G. Stoodley, Simple vector microprocessors for multimedia applications, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.25-36, November 1998, Dallas, Texas, United States
	9	Roger Espasa , Mateo Valero , James E. Smith, Out-of-order vector architectures, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.160-170, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	10	Peter Bannon. Alpha 21364: A Scalable Single-chip SMP. Technical Report htt p ://www.digit al .corn/alph ao em/ microprocessorforu m. ht m, Compaq Computer Corporation, 1998.
	11	Toni Juan , Juan J. Navarro , Olivier Temam, Data caches for superscalar processors, Proceedings of the 11th international conference on Supercomputing, p.60-67, July 07-11, 1997, Vienna, Austria [doi>10.1145/263580.263595]
	12	Jude A. Rivers , Gary S. Tyson , Edward S. Davidson , Todd M. Austin, On high-bandwidth data cache design for multi-issue processors, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.46-56, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	13	Kevin Skadron , Douglas W. Clark, Design Issues and Tradeoffs for Write Buffers, Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture, p.144, February 01-05, 1997
	14	Richard Crisp, Direct Rambus Technology: The New Main Memory Standard, IEEE Micro, v.17 n.6, p.18-28, November 1997 [doi>10.1109/40.641593]
	15	Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	16	Doug Burger and Todd Austin. The SimpleScalar Tool Set, Version 2.0. Technical Report UWCS-1342, University of Wisconsin, June 1997.
	17	Jerry D. Gibson , Toby Berger , Tom Lookabaugh , Dave Lindbergh , Richard L. Baker, Digital compression for multimedia: principles and standards, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1998
	18	Francisca Quintana, Roger Espasa, and Mateo Valero. A Case for Merging the ILP and DLP Paradigms. In Euromicro Workshop on ParalleJ and Distributed Processing. IEEE Computer Society Press, January 1998.
	19	L. I. Kontothanassis , R. A. Sugumar , G. J. Faanes , J. E. Smith , M. L. Scott, Cache performance in vector supercomputers, Proceedings of the 1994 conference on Supercomputing, p.255-264, December 1994, Washington, D.C., United States

CITED BY 10

	Francisca Quintana , Jesus Corbal , Roger Espasa , Mateo Valero, A cost effective architecture for vectorizable numerical and multimedia applications, Proceedings of the thirteenth annual ACM symposium on Parallel algorithms and architectures, p.103-112, July 2001, Crete Island, Greece
	Jesus Corbal , Roger Espasa , Mateo Valero, MOM: a matrix SIMD instruction set architecture for multimedia applications, Proceedings of the 1999 ACM/IEEE conference on Supercomputing (CDROM), p.15-es, November 14-19, 1999, Portland, Oregon, United States
	Jesus Corbal , Mateo Valero , Roger Espasa, Exploiting a new level of DLP in multimedia applications, Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.72-79, November 16-18, 1999, Haifa, Israel
	Jesus Corbal , Roger Espasa , Mateo Valero, Three-dimensional memory vectorization for high bandwidth media memory systems, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Roger Espasa , Federico Ardanaz , Joel Emer , Stephen Felix , Julio Gago , Roger Gramunt , Isaac Hernandez , Toni Juan , Geoff Lowney , Matthew Mattina , André Seznec, Tarantula: a vector extension to the alpha architecture, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
	Jeff H. Derby , Robert K. Montoye , José Moreira, VICTORIA: VMX indirect compute technology oriented towards in-line acceleration, Proceedings of the 3rd conference on Computing frontiers, May 03-05, 2006, Ischia, Italy
	Mark Hampton , Krste Asanović, Implementing virtual memory in a vector processor with software restart markers, Proceedings of the 20th annual international conference on Supercomputing, June 28-July 01, 2006, Cairns, Queensland, Australia
	Christophe Lemuet , Jack Sampson , Jean-Francois Collard , Norm Jouppi, Architecture---The potential energy efficiency of vector acceleration, Proceedings of the 2006 ACM/IEEE conference on Supercomputing, November 11-17, 2006, Tampa, Florida
	Ruchira Sasanka , Man-Lap Li , Sarita V. Adve , Yen-Kuang Chen , Eric Debes, ALP: Efficient support for all levels of parallelism for complex media applications, ACM Transactions on Architecture and Code Optimization (TACO), v.4 n.1, p.3-es, March 2007
	Joe Gebis , David Patterson, Embracing and Extending 20th-Century Instruction Set Architectures, Computer, v.40 n.4, p.68-75, April 2007