Parallel logic and fault simulation algorithms for shared memory vector machines

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Parallel logic and fault simulation algorithms for shared memory vector machines

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International Conference on Computer Aided Design archive
Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 369 - 372

Year of Publication: 1992

ISBN:0-89791-540-2

Authors

Abdulla Bataineh	Cray Research Inc., Eagan, MN
Füsun Özgüner	Dept. of Electrical Eng., The Ohio State University, Columbus, OH
Imre Szauter	AT&T Bell Laboratories, Columbus, OH

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 6, Citation Count: 3

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	F. Brglez, and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran," Proceedings of IEEE Int. Symp. Circuits Sysl.; Special Session on ATPG and Fault Simulation, Jun. 1985.
	2	R. Daoud, and F. Ozgiiner, "Highly vectorizable fault simulation on the Cray X-MP supercomputer," IEEE Trans. on Computer-Aided Design, Vol. 8, pp. 1362-1365, Dec. 1989.
	3	Monty M. Denneau, The Yorktown Simulation Engine, Proceedings of the 19th conference on Design automation, p.55-59, January 1982
	4	D. L. Greer, "The quick simulator benchmark ," VLSI Systems Design , pp. 2-7, Nov. 1987.
	5	N. Ishiura, It. Yasuura, and S. Yajima, "Highspeed logic simulation on vector processors ," IEEE Trans. on Computer-Aided Design, Vol. Cad-6, pp. 305-320, May. 1987.
	6	Y. Levendel , P. R. Menon, Fault simulation, Fault-tolerant computing: theory and techniques; vol. 1, Prentice-Hall, Inc., Upper Saddle River, NJ, 1986
	7	F. Ozguner , C. Aykanat , O. Khalid, Logic fault simulation on a vector hypercube multiprocessor, Proceedings of the third conference on Hypercube concurrent computers and applications, p.1108-1116, January 1989, Pasadena, California, United States [doi>10.1145/63047.63064]
	8	Shigeru Takasaki , Fumiyaki Hirose , Akihiko Yamada, Logic Simulation Engines in Japan, IEEE Design & Test, v.6 n.5, p.40-49, September 1989 [doi>10.1109/54.43078]

CITED BY 3

	Takaharu Nagumo , Masahiko Nagai , Takao Nishida , Masayuki Miyoshi , Shunsuke Miyamoto, VFSIM: vectorized fault simulator using a reduction technique excluding temporarily unobservable faults, Proceedings of the 31st annual conference on Design automation, p.510-515, June 06-10, 1994, San Diego, California, United States
	Minesh B. Amin , Bapiraju Vinnakota, Zamlog: a parallel algorithm for fault simulation based on Zambezi, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.509-512, November 10-14, 1996, San Jose, California, United States
	Mary L. Bailey , Jack V. Briner, Jr. , Roger D. Chamberlain, Parallel logic simulation of VLSI systems, ACM Computing Surveys (CSUR), v.26 n.3, p.255-294, Sept. 1994