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CRIS: a test cultivation program for sequential VLSI circuits

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International Conference on Computer Aided Design archive
Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 216 - 219

Year of Publication: 1992

ISBN:0-89791-540-2

Authors

Daniel G. Saab	Department of Computer Science, University of Missouri, Columbia, Missouri
Youssef G. Saab
Jacob A. Abraham	Computer Engineering, Research Center, University of Texas at Austin, Austin, TX

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 3, Citation Count: 27

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H-K. T. Ma, S. Devadas, A. R. Newton, and A. Sangiovani-Vicentelli, "Test Generation for Sequential Circuits," IEEE, Transactions on Computer Aided- Design., vol. CAD-7, pp. 1081-1093, Oct. 1988.
	2	Thomas Niermann , Janak H. Patel, HITEC: a test generation package for sequential circuits, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
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	4	Miron Abramovici, Melvin A. Breuer, and Arthur D. Friedman, Digital Systems Testing and Testable Design. NewYork: Computer Science Press, 1990.
	5	J. Galiay et al., "Physical Versus Logic Fault Models in MOS LSI Circuits, Impact on their Testability," Int. Syrup. Fault Tolerant Computing, pp. 195-202, 1979..
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	8	Madhukar K. Reddy , Sudhakar M. Reddy , Prathima Agrawal, Transistor level test generation for MOS circuits, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.825-828, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.318007]
	9	S. Seshu and D. N. Freeman, "The diagnosis of asynchronous sequential switching systems," IRE Transactions on Electronic Computing, vol. EC-11, pp. 459-465, August 1962.
	10	Kwang-Ting Cheng , Vishwani D. Agrawal, Unified Methods for VLSI Simulation and Test Generation, Kluwer Academic Publishers, Norwell, MA, 1989
	11	David E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1989
	12	F. Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," in Proceedings of the 1989 Int. Syrup. on Circuits and Systems, Portland, Oregon, May 1989.
	13	J.P. Cohoon and W. D. Paris, "Genetic Placement," in Proc. of the IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pp. 422-425, November 1986.
	14	F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran," Proc. of the Int. Test Conf., pp. 785-794, 1985.

CITED BY 27

	Dinos Moundanos , Jacob A. Abraham, On Design Validation Using Verification Technology, Journal of Electronic Testing: Theory and Applications, v.15 n.1-2, p.173-189, August-October 1999
	Elizabeth M. Rudnick , Janak H. Patel, Combining deterministic and genetic approaches for sequential circuit test generation, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.183-188, June 12-16, 1995, San Francisco, California, United States
	Fulvio Corno , Paolo prinetto , Maurizio Rebaudenpgo , Matteo Sonza Reorda, SAARA: a simulated annealing algorithm for test pattern generation for digital circuits, Proceedings of the 1997 ACM symposium on Applied computing, p.228-232, April 1997, San Jose, California, United States
	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, K2: an estimator for peak sustainable power of VLSI circuits, Proceedings of the 1997 international symposium on Low power electronics and design, p.178-183, August 18-20, 1997, Monterey, California, United States
	E. M. Rudnick , R. Vietti , A. Ellis , F. Corno , P. Prinetto , M. Sonza Reorda, Fast sequential circuit test generation using high-level and gate-level techniques, Proceedings of the conference on Design, automation and test in Europe, p.570-576, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Ben Mathew , Daniel G. Saab, Augmented partial reset, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.716-719, November 07-11, 1993, Santa Clara, California, United States
	Ruifeng Guo , Sudhakar M. Reddy , Irith Pomeranz, Proptest: a property based test pattern generator for sequential circuits using test compaction, Proceedings of the 36th ACM/IEEE conference on Design automation, p.653-659, June 21-25, 1999, New Orleans, Louisiana, United States
	Irith Pomeranz , Sudhakar M. Reddy, On static compaction of test sequences for synchronous sequential circuits, Proceedings of the 33rd annual conference on Design automation, p.215-220, June 03-07, 1996, Las Vegas, Nevada, United States
	Kwang-Ting Cheng, Gate-level test generation for sequential circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.4, p.405-442, Oct. 1996
	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, Dynamic state traversal for sequential circuit test generation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.548-565, July 2000
	Daniel G. Saab , Youssef G. Saab , Jacob A. Abraham, Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.40-43, November 06-10, 1994, San Jose, California, United States
	Ilker Hamzaoglu , Janak H. Patel, Deterministic test pattern generation techniques for sequential circuits, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Shuo Sheng , Michael S. Hsiao, Efficient Sequential Test Generation Based on Logic Simulation, IEEE Design & Test, v.19 n.5, p.56-64, September 2002
	Xijiang Lin , Irith Pomeranz , Sudhakar M. Reddy, Techniques for improving the efficiency of sequential circuit test generation, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.147-151, November 07-11, 1999, San Jose, California, United States
	Elizabeth M. Rudnick , Janak H. Patel , Gary S. Greenstein , Thomas M. Niermann, Sequential circuit test generation in a genetic algorithm framework, Proceedings of the 31st annual conference on Design automation, p.698-704, June 06-10, 1994, San Diego, California, United States
	Benjamin W. Wah , Arthur Ieumwananonthachai , Lon-Chan Chu , Akiko N. Aizawa, Genetics-Based Learning of New Heuristics: Rational Scheduling of Experiments and Generalization, IEEE Transactions on Knowledge and Data Engineering, v.7 n.5, p.763-785, October 1995
	Irith Pomeranz , Sudhakar M. Reddy, Simulation based test generation for scan designs, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Irith Pomeranz , Sudhakar M. Reddy, A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n$n$-Detections in Combinational Circuits, IEEE Transactions on Computers, v.48 n.10, p.1145-1152, October 1999
	Irith Pomeranz , Sudhakar M. Reddy, Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits, IEEE Transactions on Computers, v.49 n.6, p.596-607, June 2000
	Bernd Becker , Martin Keim , Rolf Krieger, Hybrid Fault Simulation for Synchronous Sequential Circuits, Journal of Electronic Testing: Theory and Applications, v.15 n.3, p.219-238, Dec. 1999
	Jano I. van Hemert, Evolving combinatorial problem instances that are difficult to solve, Evolutionary Computation, v.14 n.4, p.433-462, December 2006
	Irith Pomeranz , Sudhakar M. Reddy, On test generation by input cube avoidance, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Huy Nguyen , Rabindra Roy , Abhijit Chatterjee, Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits, Journal of Electronic Testing: Theory and Applications, v.14 n.3, p.259-272, June 1999
	Jian Shen , Jacob A. Abraham, Synthesis of Native Mode Self-Test Programs, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.137-148, Oct. 1998
	Jalal A. Wehbeh , Daniel G. Saab, Initialization of Sequential Circuits and its Application to ATPG, Journal of Electronic Testing: Theory and Applications, v.13 n.3, p.259-271, Dec. 1998
	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, Sequential Circuit Test Generation Using Dynamic State Traversal, Proceedings of the 1997 European conference on Design and Test, p.22, March 17-20, 1997
	I. Pomeranz , S. M. Reddy, On improving genetic optimization based test generation, Proceedings of the 1997 European conference on Design and Test, p.506, March 17-20, 1997