| Automatic compositional minimization in CTL model checking |
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International Conference on Computer Aided Design
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Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
table of contents
Santa Clara, California, United States
Pages: 172 - 178
Year of Publication: 1992
ISBN:0-89791-540-2
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Authors
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Massimiliano Chiodo
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Magneti Marelli, Pavia, Italy
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Thomas R. Shiple
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Department of EECS, University of California, Berkeley, CA
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Alberto L. Sangiovanni-Vincentelli
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Department of EECS, University of California, Berkeley, CA
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Robert K. Brayton
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Department of EECS, University of California, Berkeley, CA
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IEEE Computer Society Press
Los Alamitos, CA, USA
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| Bibliometrics |
Downloads (6 Weeks): 1, Downloads (12 Months): 7, Citation Count: 5
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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D. Arnett, "A High Performance Solution for In-Vehicle Networking - 'Controller Area Network (CAN),"' SAE Technical Paper Series, 870823, Apr. 1987.
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3
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J. R. Burch , E. M. Clarke , K. L. McMillan , David L. Dill, Sequential circuit verification using symbolic model checking, Proceedings of the 27th ACM/IEEE conference on Design automation, p.46-51, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123223]
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4
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J. R. Burch , E. M. Clarke , D. E. Long, Representing circuits more efficiently in symbolic model checking, Proceedings of the 28th conference on ACM/IEEE design automation, p.403-407, June 17-22, 1991, San Francisco, California, United States
[doi> 10.1145/127601.127702]
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M. Chiodo, T. R. Shiple, A. Sangiovanni-Vincentelli, and R. K. Brayton, "Automatic Reduction in CTL Compositional Model Checking," Memorandum No. UCB/ERL M92/55, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, Jan. 1992.
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Edmund M. Clarke , Orna Grumberg , David E. Long, Model checking and abstraction, Proceedings of the 19th ACM SIGPLAN-SIGACT symposium on Principles of programming languages, p.343-354, January 19-22, 1992, Albuquerque, New Mexico, United States
[doi> 10.1145/143165.143235]
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J. E. Hopcroft, "An n log n Algorithm for Minimizing the States in a Finite Automaton," in The Theory of Machines and Computation, New York: Academic Press, pp. 189-196, 1971.
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15
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Z. Manna and A. Pneuli, "Verification of Concurrent Programs: The Temporal Framework," in The Correctness Problem in Computer Science, editors R. S. Boyer and J. Strother Moore, Int. Lecture Series in Computer Science, London: Academic Press, pp. 215-273, 1981.
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Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
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H. J. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. S angiovanni-Vincentelli, "Implicit State Enumeration of Finite State Machines using BDDs," in Proc. oflEEE International Conference on Computer-Aided Design, pp. 130-133, Nov. 1990.
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CITED BY 5
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Alan J. Hu , Gary York , David L. Dill, New techniques for efficient verification with implicitly conjoined BDDs, Proceedings of the 31st annual conference on Design automation, p.276-282, June 06-10, 1994, San Diego, California, United States
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Alberto L. Sangiovanni-Vincentelli , Patrick C. McGeer , Alexander Saldanha, Verification of electronic systems, Proceedings of the 33rd annual conference on Design automation, p.106-111, June 03-07, 1996, Las Vegas, Nevada, United States
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