An optimal chip compaction method based on shortest path algorithm with automatic jog insertion

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An optimal chip compaction method based on shortest path algorithm with automatic jog insertion

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International Conference on Computer Aided Design archive
Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 162 - 165

Year of Publication: 1992

ISBN:0-89791-540-2

Authors

Toru Awashima	Department of Electronics and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169, Japan
Wataru Yamamoto	Central Research Lab., Hitachi Ltd. and Department of Electronics and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169, Japan
Masao Sato	Department of Electronics and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169, Japan
Tatsuo Ohtsuki	Department of Electronics and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169, Japan

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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