Graph algorithms for clock schedule optimization

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Graph algorithms for clock schedule optimization

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International Conference on Computer Aided Design archive
Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 132 - 136

Year of Publication: 1992

ISBN:0-89791-540-2

Authors

Narendra Shenoy	Department of EECS, University of California, Berkeley, CA
Robert K. Brayton	Department of EECS, University of California, Berkeley, CA
Alberto L. Sangiovanni-Vincentelli	Department of EECS, University of California, Berkeley, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 16, Citation Count: 18

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	8	Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
	9	N. Shenoy, R. K. Brayton, and A. L. Sangiovanni- Vincentelli. Graph Algorithms for Clock Schedule Optimization. Technical report, University of California, Technical Report UCB/ERL M92/79, 1992.
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	14	N. Weiner , A. Sangiovanni-Vincentelli, Timing analysis in a logic synthesis environment, Proceedings of the 26th ACM/IEEE conference on Design automation, p.655-661, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74498]

CITED BY 18

	Narendra V. Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Resynthesis of multi-phase pipelines, Proceedings of the 30th international conference on Design automation, p.490-496, June 14-18, 1993, Dallas, Texas, United States
	José Luis Neves , Eby G. Friedman, Optimal clock skew scheduling tolerant to process variations, Proceedings of the 33rd annual conference on Design automation, p.623-628, June 03-07, 1996, Las Vegas, Nevada, United States
	Chung-wen Albert Tsao , Cheng-kok Koh, UST/DME: a clock tree router for general skew constraints, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.3, p.359-379, July 2002
	Ashok Vittal , Hein Ha , Forrest Brewer , Malgorzata Marek-Sadowska, Clock skew optimization for ground bounce control, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.395-399, November 10-14, 1996, San Jose, California, United States
	C. Albrecht , B. Korte , J. Schietke , J. Vygen, Cycle time and slack optimization for VLSI-chips, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.232-238, November 07-11, 1999, San Jose, California, United States
	Ivan S. Kourtev , Eby G. Friedman, Clock skew scheduling for improved reliability via quadratic programming, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.239-243, November 07-11, 1999, San Jose, California, United States
	Jin-fuw Lee , Donald T. Tang , C. K. Wong, A timing analysis algorithm for circuits with level-sensitive latches, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.743-748, November 06-10, 1994, San Jose, California, United States
	P. Vuillod , L. Benini , A. Bogliolo , G. De Micheli, Clock skew optimization for peak current reduction, Proceedings of the 1996 international symposium on Low power electronics and design, p.265-270, August 12-14, 1996, Monterey, California, United States
	Chung-Wen Albert Tsao , Cheng-Kok Koh, UST/DME: a clock tree router for general skew constraints, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Baris Taskin , Ivan S. Kourtev, Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
	I-Min Liu , Tan-Li Chou , Adnan Aziz , D. F. Wong, Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion, Proceedings of the 2000 international symposium on Physical design, p.33-38, May 2000, San Diego, California, United States
	Kai Wang , Malgorzata Marek-Sadowska, Buffer sizing for clock power minimization subject to general skew constraints, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Christoph Albrecht , Bernhard Korte , Jürgen Schietke , Jens Vygen, Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip, Discrete Applied Mathematics, v.123 n.1-3, p.103-127, 15 November 2002
	Dian Zhou , Rui-Ming Li, Design and verification of high-speed VLSI physical design, Journal of Computer Science and Technology, v.20 n.2, p.147-165, March 2005
	Christoph Albrecht, Efficient incremental clock latency scheduling for large circuits, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Ruiming Chen , Hai Zhou, Clock schedule verification under process variations, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.619-625, November 07-11, 2004
	Chuan Lin , Hai Zhou, Trade-off between latch and flop for min-period sequential circuit designs with crosstalk, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.329-334, November 06-10, 2005, San Jose, CA
	Stephan Held , Bernhard Korte , Jens Maβberg , Matthias Ringe , Jens Vygen, Clock Scheduling and Clocktree Construction for High Performance ASICS, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.232, November 09-13, 2003