| Timing distribution in VHDL behavioral models |
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International Conference on Computer Aided Design
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Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
table of contents
Santa Clara, California, United States
Pages: 82 - 89
Year of Publication: 1992
ISBN:0-89791-540-2
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Authors
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Ashish S. Gadagkar
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Bradley Department of Electrical Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA
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James R. Armstrong
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Bradley Department of Electrical Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA
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IEEE Computer Society Press
Los Alamitos, CA, USA
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Downloads (6 Weeks): 3, Downloads (12 Months): 16, Citation Count: 0
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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B. Harding, "System Simulation Assures that Chips Play Together," Computer Design, 1989, Aug. 1, pp.70-84.
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P.D. Linderman, "Top-Down Design Synthesis Using VHDL," WESCON 1990, pp.382-383.
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Nikil D. Dutt , Tedd Hadley , Daniel D. Gajski, An intermediate representation for behavioral synthesis, Proceedings of the 27th ACM/IEEE conference on Design automation, p.14-19, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123192]
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13. Singh, "A Parametrized CAD tool for VHDL Model Development with X-Windows," Masters Thesis, Virginia Polytechnic Institute and State University, i990.
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H. P. Williams, "Model Building in Mathematical Programming," Wiley, New York, 1985.
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G. Hadley, "Linear Programming," Addison-Wesley, Massachussets, 1962.
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14
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T.Asano, S. Sato, "Long Path Enumeration Algorithms for Timing Verification on Large Digital Systems," 5th Quadrarmeil Infl Conf. on the Theory and Applications of Graphs with special emphasis on Algorithms and Computer Science, Michigan, June 4-8, 1984.
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