A tutorial on logic synthesis for lookup-table based FPGAs

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A tutorial on logic synthesis for lookup-table based FPGAs

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International Conference on Computer Aided Design archive
Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 40 - 47

Year of Publication: 1992

ISBN:0-89791-540-2

Author

Robert J. Francis

Department of Electrical Engineering, University of Toronto

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 13, Downloads (12 Months): 60, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Stephen D. Brown , Robert J. Francis , Jonathan Rose , Zvonko G. Vranesic, Field-programmable gate arrays, Kluwer Academic Publishers, Norwell, MA, 1992
	2	R.K. Brayton, G. D. Hachtel, A. Sangiovanni_Vincentelli, "Multilevel Logic Synthesis," Proc. of IEEE, Vol. 78, No. 2, Feb. 1990, pp. 264-300.
	3	K. Keutzer, DAGON: technology binding and local optimization by DAG matching, Proceedings of the 24th ACM/IEEE conference on Design automation, p.341-347, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37940]
	4	S, Trimberger, "A Small Complete Mapping Library for Lookup-Table-Based FPGAs," 2nd Intl. Workshop on Field-Programmable Logic and Applications, Aug. 1992.
	5	U. Schlichtmann , F. Brglez , M. Hermann, Characterization of Boolean functions for rapid matching in FPGA technology mapping, Proceedings of the 29th ACM/IEEE conference on Design automation, p.374-379, June 08-12, 1992, Anaheim, California, United States
	6	Robert J. Francis , Jonathan Rose , Kevin Chung, Chortle: a technology mapping program for lookup table-based field programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.613-619, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123418]
	7	Rajeev Murgai , Yoshihito Nishizaki , Narendra Shenoy , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, Logic synthesis for programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.620-625, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123421]
	8	P. Abouzeid, L. Bouchet, K. Sakouti, G. Saucier, P. Sicard, "Lexicographical Expression of Boolean Function for Multilevel Synthesis of high Speed Circuits," Proc. SASHIMI 90, Oct. 1990, pp. 31-39.
	9	David Filo , Jerry Chih-Yuan Yang , Frédéric Mailhot , Giovanni De Micheli, Technology mapping for a two-output RAM-based field programmable gate array, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	10	Robert Francis , Jonathan Rose , Zvonko Vranesic, Chortle-crf: Fast technology mapping for lookup table-based FPGAs, Proceedings of the 28th conference on ACM/IEEE design automation, p.227-233, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127670]
	11	Kevin Karplus, Xmap: A technology mapper for table-lookup field-programmable gate arrays, Proceedings of the 28th conference on ACM/IEEE design automation, p.240-243, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127672]
	12	Nam-Sung Woo, A heuristic method for FPGA technology mapping based on the edge visibility, Proceedings of the 28th conference on ACM/IEEE design automation, p.248-251, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127675]
	13	R. Murgai, N. Shenoy, R.K. Brayton, A. Sangiovanni- Vincentelli, "Improved Logic Synthesis Algorithms for Table Look Up Architectures," Proc. ICCAD, Nov. 1991, pp. 564-567.
	14	R.J. Francis, J, Rose, Z. Vranesic, "Technology Mapping of Lookup Table-Based FPGAs for Performance," Proc. ICCAD, Nov. 1991. pp. 568-571.
	15	R. Murgai, N. Shenoy, R.K. Brayton, "Performance Directed Synthesis for Table Look Up Programmable," Gate Arrays, Proc. ICCAD, Nov. 1991 pp. 572-575
	16	Kuang-Chien Chen , Jason Cong, Maximal reduction of lookup-table based FPGAs, Proceedings of the conference on European design automation, p.224-229, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	17	P. Sawkar , D. Thomas, Area and delay mapping for table-look-up based field programmable gate arrays, Proceedings of the 29th ACM/IEEE conference on Design automation, p.368-373, June 08-12, 1992, Anaheim, California, United States
	18	Jason Cong , Yuzheng Ding , Andrew B. Kahng , Peter Trajmar , Kuang-Chien Chen, An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.154-158, October 11-14, 1992
	19	E.J. McClusky, Logic Design Principles, Prentice Hall, 1986.
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	21	Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
	22	R.J. Francis, Technology Mapping for Lookup Table- Based :FPGAs, Ph.D. Thesis in preparation, University of Toronto, Department of Electrical Engineering.

CITED BY 2

	Jason Cong , Yuzheng Ding, Combinational logic synthesis for LUT based field programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.145-204, April 1996
	Min Xu , Fadi J. Kurdahi, Layout-driven RTL binding techniques for high-level synthesis using accurate estimators, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.4, p.312-343, Oct. 1997