Configuration of a boundary scan chain for optimal testing of clusters of non boundary scan devices

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Configuration of a boundary scan chain for optimal testing of clusters of non boundary scan devices

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International Conference on Computer Aided Design archive
Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 13 - 16

Year of Publication: 1992

ISBN:0-89791-540-2

Authors

Y.-H. Choi	Department of Computer Science, University of Minnesota, Minneapolis, MN
T. Jung	Department of Computer Science, University of Minnesota, Minneapolis, MN

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. G. Bennetts , A. Osseyran, IEEE standard 1149.1-1990 on boundary scan: history, literature survey, and current status, Journal of Electronic Testing: Theory and Applications, v.2 n.1, p.11-25, March 1991 [doi>10.1007/BF00134941]
	2	R. P. van Riessen , H. G. Kerkhoff , A. Kloppenburg, Designing and Implementing an Architecture with Boundary Scan, IEEE Design & Test, v.7 n.1, p.9-19, January 1990 [doi>10.1109/54.46889]
	3	P. Hansen, 'Testing conventional logic and memory clusters using boundary scan devices as virtual ATE channels", Int. Test Conf., pp. 166-173, 1989.
	4	Mark F. Lefebvre, Test Generation: A Boundary Scan Implementation for Module Interconnect Testing, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.88-95, October 26-30, 1991
	5	Jung-Cheun Lien , Melvin A. Breuer, An optimal scheduling algorithm for testing interconnect using boundary scan, Journal of Electronic Testing: Theory and Applications, v.2 n.1, p.117-130, March 1991 [doi>10.1007/BF00134948]