Overall consideration of scan design and test generation

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Overall consideration of scan design and test generation

Full text

Pdf (477 KB)

Source

International Conference on Computer Aided Design archive
Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 9 - 12

Year of Publication: 1992

ISBN:0-89791-540-2

Authors

Pao-Chuan Chen	Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan 70101, R.O.C.
Bin-Da Liu	Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan 70101, R.O.C.
Jhing-Fa Wang	Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan 70101, R.O.C.

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 10, Citation Count: 5

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	E. B. Eichelberger , T. W. Williams, A logic design structure for LSI testability, Proceedings of the 14th conference on Design automation, p.462-468, January 1977
	2	T.H. Chen and M. Breuer, "Automatic design for testability via testability measures," IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 3-1 i, Jan. 1985.
	3	K.S. Kim and C. R. Kime, "Partial scan by use of empirical testability," in Proc. Int. Conf on Computer-Aided Design, 1990, pp. 314-317.
	4	E. Trischler, "Incomplete scan path with an automatic test generation methodology," in Proc. Int. Test Conf., 1980, pp. 153-162.
	5	K.T. Cheng and V. D. Agrawal, "An economical scan design for sequential logic test generation," in Proc. 19th Int. Symp. on Fault-Tolerant Computing, 1989, pp. 28-35.
	6	R. Gupta and M. A. Breuer, "BALLAST: A methodology for partial scan design," in Proc. 19th Int. Symp. on Fault-Tolerant Computing, 1989, pp. 118-125.
	7	D.H. Lee and S. M. Reddy, "On determining scan flipflops in partial scan design," in Proc. Int. Conf on Computer-Aided Design, 1990, pp. 322-325.
	8	V. Chickermane and J. H. Patel, "A fault oriented partial scan design approach", in Proc. Int. Conf on Computer-Aided Desisn, 1991, pp. 400-403.
	9	V.D. Agrawal, K. T. Cheng, D. D. Johnson and T. Lin, "A complete solution to the partial scan problem," in Proc. Int. Test Conf., 1987, pp. 44-51.
	10	H. K. T. Ma, S. Devadas, A. R. Newton and A. Sangiovanni-Vincentelli, "An incomplete scan design approach to test generation for sequential machines," in Proc. Int. Test Conf., 1988, pp. 730- 734.
	11	P. C. Chen, J. F. Wang and B. D. Liu, "Gradually-on structure for scan design,", Electronic Letters, Vol. 28, pp. 868-869, Apr. 1992.
	12	Prabhakar Goel , Barry C. Rosales, PODEM-X: An automatic test generation system for VLSI logic structures, Proceedings of the 18th conference on Design automation, p.260-268, June 29-July 01, 1981, Nashville, Tennessee, United States
	13	P. Goel, "An implicit enumeration algorithm to generate tests for combination logic circuits," iEEE Trans. Comput., Vol.c-30, pp.215-222, Mar. 1981.
	14	T., Kelsey and K. Saluja, "Fast test generation for sequential circuits," in Proc. Int. Conf. on Computer- Aided Design, 1989, pp. 354-357.

CITED BY 5

	Irith Pomeranz, Random limited-scan to improve random pattern testing of scan circuits, Proceedings of the 38th conference on Design automation, p.145-150, June 2001, Las Vegas, Nevada, United States
	Irith Pomeranz , Sudhakar M. Reddy, Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.780-788, July 2004
	Irith Pomeranz , Sudhakar M. Reddy, Static Test Compaction for Scan-Based Designs to Reduce Test Application Time, Journal of Electronic Testing: Theory and Applications, v.16 n.5, p.541-552, Oct 2000
	Irith Pomeranz , Sudhakar M. Reddy, Test compaction for transition faults under transparent-scan, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Irith Pomeranz , Sudhakar M. Reddy, A New Approach to Test Generation and Test Compaction for Scan Circuits, Proceedings of the conference on Design, Automation and Test in Europe, p.11000, March 03-07, 2003