An architectural perspective on a memory access controller

ABSTRACT

In this paper a CMOS memory access controller chip is described that provides the basis for achieving high-performance 68020-based (68030-based) systems. This controller matches the speed of the memory system to that of the microprocessor by providing a virtual cache mechanism where address translations are only required when there is a cache miss. This mechanism also facilitates the construction of shared-memory multiprocessor system where the controller manages a memory hierarchy consisting of cache memory, local memory, and shared global memory.

REFERENCES

• 1: J. S. Liptay, "Structural Aspects of the System/360 Model 85: The Cache," IBM Journal of Research and Development, vol. 7, no. 1, 1968, pp 15-21.
• 2: C. J. Conti, "Concepts for Buffer Storage," Computer Group News, March 1969, pp 9-13.
• 3: M. V. Wilkes, "Slave Memories and Dynamic Storage Allocation," IEEE Transactions on Computers, vol. C-14, April 1965, pp 270-271.
• 4: Mark D. Hill , Alan Jay Smith, Experimental evaluation of on-chip microprocessor cache memories, Proceedings of the 11th annual international symposium on Computer architecture, p.158-166, January 1984
• 5: Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982 [doi>10.1145/356887.356892]
• 6: J. Moussouris, L. Crudele, D. Freitas, C. Hansen, E. Hudson, R. March, S. Przybylski, T. Riordan, C. Rowen, D. Van't Hof, "A CMOS RISC Processor with Integrated System Functions," Proceedings of COMPCON Spring 86, March 1986, pp 126-131.
• 7: DEC VAX 11/780 Architecture Handbook, Digital Equipment Corporation, Maynard, Massachusetts, 1979.
• 8: D. C. Evans & J. Y. LeClerc, "Address Mappings and the Control of Access in an Interactive Computer," AFIPS Conference Proceedings Spring Joint Computer Conference, 1967, vol. 30, pp 23-30.
• 9: Cedell A. Alexander , William M. Keshlear , Faye Briggs, Translation buffer performance in a UNIX enviroment, ACM SIGARCH Computer Architecture News, v.13 n.5, p.2-14, Dec 1 1985 [doi>10.1145/381757.381758]
• 10: R. L. Norton & J. A. Abraham, "Using Write Back Cache to Improve Performance of Multiuser Multiprocessors," Proceedings of the 1982 International Conference on Parallel Processing, August 1982, pp 326-331.
• 11: P. Sweazey , A. J. Smith, A class of compatible cache consistency protocols and their support by the IEEE futurebus, Proceedings of the 13th annual international symposium on Computer architecture, p.414-423, June 02-05, 1986, Tokyo, Japan
• 12: James Archibald , Jean-Loup Baer, Cache coherence protocols: evaluation using a multiprocessor simulation model, ACM Transactions on Computer Systems (TOCS), v.4 n.4, p.273-298, Nov. 1986 [doi>10.1145/6513.6514]
• 13: Cedell Alexander , William Keshlear , Furrokh Cooper , Faye Briggs, Cache memory performance in a unix enviroment, ACM SIGARCH Computer Architecture News, v.14 n.3, p.41-61, June 1 1986 [doi>10.1145/381711.381717]
• 14: A. J. Smith, Line (block) size choice for CPU cache memories, IEEE Transactions on Computers, v.36 n.9, p.1063-1076, Sept. 1987 [doi>10.1109/TC.1987.5009537]
• 15: David R. Ditzel , H. R. McLellan, Register allocation for free: The C machine stack cache, Proceedings of the first international symposium on Architectural support for programming languages and operating systems, p.48-56, March 01-03, 1982, Palo Alto, California, United States
• 16: M. Freeman & C. Kaplinsky, "Modeling the Resources of a System Demonstrates Memory Controller's Power," Electronic Design, September 1984.
• 17: Richard E. Matick, Computer Storage Systems and Technology, John Wiley & Sons, Inc., New York, NY, 1977
• 18: John L. Hennessy , Mark A. Horowitz, An overview of the MIPS-X-MP project, Stanford University, Stanford, CA, 1986
• 19: D. R. Cheriton , G. A. Slavenburg , P. D. Boyle, Software-controlled caches in the VMP multiprocessor, Proceedings of the 13th annual international symposium on Computer architecture, p.366-374, June 02-05, 1986, Tokyo, Japan

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies

  C. Computer Systems Organization

General Terms:
Design, Measurement, Performance